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author | Andrew Lukefahr <lukefahr@umich.edu> | 2014-11-06 05:42:21 -0600 |
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committer | Andrew Lukefahr <lukefahr@umich.edu> | 2014-11-06 05:42:21 -0600 |
commit | bd32d55a2c457e7e68c1462d05fa126aa131a21a (patch) | |
tree | d0455fdf65c3de7d87f3163f2ec5563035bf30a1 /src/arch/x86/isa | |
parent | a75e27b4a64df780e9b8207e10f3a11f172d1db3 (diff) | |
download | gem5-bd32d55a2c457e7e68c1462d05fa126aa131a21a.tar.xz |
cpu: Minor Draining Bug
Fixes a bug where Minor drains in the midst of committing a
conditional store.
While committing a conditional store, lastCommitWasEndOfMacroop is true
(from the previous instruction) as we still haven't finished the conditional
store. If a drain occurs before the cache response, Minor would check just
lastCommitWasEndOfMacroop, which was true, and set drainState=DrainHaltFetch,
which increases the streamSeqNum. This caused the conditional store to be
squashed when the memory responded and it completed. However, to the memory
the store succeeded, while to the instruction sequence it never occurred.
In the case of an LLSC, the instruction sequence will replay the squashed
STREX, which will fail as the cache is no longer in LLSC. Then the
instruction sequence will loop back to a LDREX, which receives the updated
(incorrect) value.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/arch/x86/isa')
0 files changed, 0 insertions, 0 deletions