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authorGabe Black <gblack@eecs.umich.edu>2007-12-01 23:00:15 -0800
committerGabe Black <gblack@eecs.umich.edu>2007-12-01 23:00:15 -0800
commitbfc62d1a7035dfdbad405c0ddbd897ea1174360d (patch)
tree1fa01d23200823c1e162d28303254b81bccea6f3 /src/arch/x86/isa
parent7433032b39828ccff9ad5ed0e3ed95f752fc269a (diff)
downloadgem5-bfc62d1a7035dfdbad405c0ddbd897ea1174360d.tar.xz
X86: Separate the effective seg base and the "hidden" seg base.
--HG-- extra : convert_revision : 5fcb8d94dbab7a7d6fe797277a5856903c885ad4
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/operands.isa4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index f50e71727..7a2631a9c 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -121,11 +121,11 @@ def operands {{
# The TOP register should needs to be more protected so that later
# instructions don't map their indexes with an old value.
'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 61),
- 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
+ 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_EFF_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
'ControlDest': ('ControlReg', 'uqw', 'MISCREG_CR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 71),
'ControlSrc1': ('ControlReg', 'uqw', 'MISCREG_CR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 72),
'EferOp': ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 73),
'CR4Op': ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 74),
- 'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
+ 'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
}};