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authorGabe Black <gblack@eecs.umich.edu>2009-08-17 20:25:13 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-08-17 20:25:13 -0700
commitb315c3effc89127017c34b55908e7e63adca3f11 (patch)
tree0673781b12ea95b6e7d97aae0277c38e9b785611 /src/arch/x86/isa
parent7fbd9e12961aaee1c81e723c4d40b70d5108845e (diff)
downloadgem5-b315c3effc89127017c34b55908e7e63adca3f11.tar.xz
X86: Implement STMXCSR.
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa2
-rw-r--r--src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py11
2 files changed, 11 insertions, 2 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 7d955eb3e..5d817d2c2 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -829,7 +829,7 @@
0x0: fxsave();
0x1: fxrstor();
0x2: ldmxcsr();
- 0x3: stmxcsr();
+ 0x3: Inst::STMXCSR(Md);
0x4: Inst::UD2();
0x5: decode MODRM_MOD {
0x3: BasicOperate::LFENCE(
diff --git a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
index 687391b47..831a266c7 100644
--- a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
+++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
@@ -54,6 +54,15 @@
# Authors: Gabe Black
microcode = '''
-# STMXCSR
+def macroop STMXCSR_M {
+ rdval t1, "InstRegIndex(MISCREG_MXCSR)"
+ st t1, seg, sib, disp
+};
+
+def macroop STMXCSR_P {
+ rdval t1, "InstRegIndex(MISCREG_MXCSR)"
+ rdip t7
+ st t1, seg, riprel, disp
+};
# LDMXCSR
'''