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authorChristian Menard <christian.menard@tu-dresden.de>2013-11-26 17:51:07 +0100
committerChristian Menard <christian.menard@tu-dresden.de>2013-11-26 17:51:07 +0100
commitd4f205ea2ff2800b253d4681afaa6af330bfa33b (patch)
tree91a4849143127b37fa3d536aca32ea8074615ad1 /src/arch/x86/isa
parente5d63d05354b7dc03b35e99d1f7b5aa80ec6fff5 (diff)
downloadgem5-d4f205ea2ff2800b253d4681afaa6af330bfa33b.tar.xz
x86: Implementation of Int3 and Int_Ib in long mode
This is an implementation of the x86 int3 and int immediate instructions for long mode according to 'AMD64 Programmers Manual Volume 3'.
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/decoder/one_byte_opcodes.isa6
-rw-r--r--src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py28
2 files changed, 32 insertions, 2 deletions
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index a6173831c..92e5cd0a8 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -393,8 +393,8 @@
0x3, 0x4: ret_far_real();
default: Inst::RET_FAR();
}
- 0x4: int3();
- 0x5: decode FullSystemInt default int_Ib() {
+ 0x4: Inst::INT3();
+ 0x5: decode FullSystemInt default inst_ib() {
0: decode IMMEDIATE {
// Really only the LSB matters, but the decoder
// will sign extend it, and there's no easy way to
@@ -403,6 +403,8 @@
SyscallInst::int80('xc->syscall(Rax)',
IsSyscall, IsNonSpeculative, IsSerializeAfter);
}
+
+ default: Inst::INT(Ib);
}
0x6: decode MODE_SUBMODE {
0x0: Inst::UD2();
diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
index 19a344008..d50e40e61 100644
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
@@ -221,6 +221,34 @@ skipSegmentSquashing:
def macroop IRET_VIRT {
panic "Virtual mode iret isn't implemented!"
};
+
+def macroop INT3 {
+
+ limm t1, 0x03, dataSize=8
+
+ rdip t7
+
+ # Are we in long mode?
+ rdm5reg t5
+ andi t0, t5, 0x1, flags=(EZF,)
+ br rom_label("longModeSoftInterrupt"), flags=(CEZF,)
+ br rom_label("legacyModeInterrupt")
+};
+
+def macroop INT_I {
+
+ #load the byte-sized interrupt vector specified in the instruction
+ .adjust_imm trimImm(8)
+ limm t1, imm, dataSize=8
+
+ rdip t7
+
+ # Are we in long mode?
+ rdm5reg t5
+ andi t0, t5, 0x1, flags=(EZF,)
+ br rom_label("longModeSoftInterrupt"), flags=(CEZF,)
+ br rom_label("legacyModeInterrupt")
+};
'''
#let {{
# class INT(Inst):