Merge python and x86 changes with cache branch

--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233

16 files changed, 1331 insertions, 295 deletions

diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index b28f2029c..3b51f9d73 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -72,7 +72,7 @@
             default: MultiInst::ADD(OPCODE_OP_BOTTOM3,
                                     [Eb,Gb], [Ev,Gv],
                                     [Gb,Eb], [Gv,Ev],
-                                    [rAl,Ib], [rAx,Iz]);
+                                    [rAb,Ib], [rAv,Iz]);
         }
         0x01: decode OPCODE_OP_BOTTOM3 {
             0x6: decode MODE_SUBMODE {
@@ -85,7 +85,7 @@
             default: MultiInst::OR(OPCODE_OP_BOTTOM3,
                                    [Eb,Gb], [Ev,Gv],
                                    [Gb,Eb], [Gv,Ev],
-                                   [rAl,Ib], [rAx,Iz]);
+                                   [rAb,Ib], [rAv,Iz]);
         }
         0x02: decode OPCODE_OP_BOTTOM3 {
             0x6: decode MODE_SUBMODE {
@@ -99,7 +99,7 @@
             default: MultiInst::ADC(OPCODE_OP_BOTTOM3,
                                     [Eb,Gb], [Ev,Gv],
                                     [Gb,Eb], [Gv,Ev],
-                                    [rAl,Ib], [rAx,Iz]);
+                                    [rAb,Ib], [rAv,Iz]);
         }
         0x03: decode OPCODE_OP_BOTTOM3 {
             0x6: decode MODE_SUBMODE {
@@ -113,7 +113,7 @@
             default: MultiInst::SBB(OPCODE_OP_BOTTOM3,
                                     [Eb,Gb], [Ev,Gv],
                                     [Gb,Eb], [Gv,Ev],
-                                    [rAl,Ib], [rAx,Iz]);
+                                    [rAb,Ib], [rAv,Iz]);
         }
         0x04: decode OPCODE_OP_BOTTOM3 {
             0x6: M5InternalError::error(
@@ -125,7 +125,7 @@
             default: MultiInst::AND(OPCODE_OP_BOTTOM3,
                                     [Eb,Gb], [Ev,Gv],
                                     [Gb,Eb], [Gv,Ev],
-                                    [rAl,Ib], [rAx,Iz]);
+                                    [rAb,Ib], [rAv,Iz]);
         }
         0x05: decode OPCODE_OP_BOTTOM3 {
             0x6: M5InternalError::error(
@@ -134,7 +134,7 @@
             default: MultiInst::SUB(OPCODE_OP_BOTTOM3,
                                     [Eb,Gb], [Ev,Gv],
                                     [Gb,Eb], [Gv,Ev],
-                                    [rAl,Ib], [rAx,Iz]);
+                                    [rAb,Ib], [rAv,Iz]);
         }
         0x06: decode OPCODE_OP_BOTTOM3 {
             0x6: M5InternalError::error(
@@ -146,7 +146,7 @@
             default: MultiInst::XOR(OPCODE_OP_BOTTOM3,
                                     [Eb,Gb], [Ev,Gv],
                                     [Gb,Eb], [Gv,Ev],
-                                    [rAl,Ib], [rAx,Iz]);
+                                    [rAb,Ib], [rAv,Iz]);
         }
         0x07: decode OPCODE_OP_BOTTOM3 {
             0x6: M5InternalError::error(
@@ -158,37 +158,40 @@
             default: MultiInst::CMP(OPCODE_OP_BOTTOM3,
                                     [Eb,Gb], [Ev,Gv],
                                     [Gb,Eb], [Gv,Ev],
-                                    [rAl,Ib], [rAx,Iz]);
-        }
-        0x08: decode MODE_SUBMODE {
-            0x0: M5InternalError::error (
-                {{"Tried to execute an REX prefix!"}});
-            default: Inst::INC(B);
-        }
-        0x09: decode MODE_SUBMODE {
-            0x0: M5InternalError::error (
-                {{"Tried to execute an REX prefix!"}});
-            default: Inst::DEC(B);
+                                    [rAb,Ib], [rAv,Iz]);
         }
         format Inst {
-            0x0A: PUSH(B);
-            0x0B: POP(B);
+            0x08: decode MODE_SUBMODE {
+                0x0: M5InternalError::error (
+                    {{"Tried to execute an REX prefix!"}});
+                default: INC(Bv);
+            }
+            0x09: decode MODE_SUBMODE {
+                0x0: M5InternalError::error (
+                    {{"Tried to execute an REX prefix!"}});
+                default: DEC(Bv);
+            }
+            0x0A: PUSH(Bv);
+            0x0B: POP(Bv);
         }
         0x0C: decode OPCODE_OP_BOTTOM3 {
             0x0: decode MODE_SUBMODE {
                 0x0: Inst::UD2();
-                default: pusha();
+                default: Inst::PUSHA();
             }
             0x1: decode MODE_SUBMODE {
                 0x0: Inst::UD2();
-                default: popa();
+                default: Inst::POPA();
             }
             0x2: decode MODE_SUBMODE {
                 0x0: Inst::UD2();
                 default: bound_Gv_Ma();
             }
             0x3: decode MODE_SUBMODE {
-                0x0: Inst::MOVSXD(Gv,Ed);
+                //The second operand should really be of size "d", but it's
+                //set to "v" in order to have a consistent register size.
+                //This shouldn't affect behavior.
+                0x0: Inst::MOVSXD(Gv,Ev);
                 default: arpl_Ew_Gw();
             }
             0x4: M5InternalError::error(
@@ -201,10 +204,10 @@
                 {{"Tried to execute the DS address size override prefix!"}});
         }
         0x0D: decode OPCODE_OP_BOTTOM3 {
-            0x0: push_Iz();
-            0x1: imul_Gv_Ev_Iz();
-            0x2: push_Ib();
-            0x3: imul_Gv_Ev_Ib();
+            0x0: Inst::PUSH(Iz);
+            0x1: Inst::IMUL(Gv,Ev,Iz);
+            0x2: Inst::PUSH(Ib);
+            0x3: Inst::IMUL(Gv,Ev,Ib);
             0x4: ins_Yb_Dx();
             0x5: ins_Yz_Dx();
             0x6: outs_Dx_Xb();
@@ -302,8 +305,8 @@
             default: xchg_B_rAX();
         }
         0x13: decode OPCODE_OP_BOTTOM3 {
-            0x0: cbw_or_cwde_or_cdqe_rAX();
-            0x1: cwd_or_cdq_or_cqo_rAX_rDX();
+            0x0: Inst::CDQE(rAv);
+            0x1: Inst::CQO(rAv,rDv);
             0x2: decode MODE_SUBMODE {
                 0x0: Inst::UD2();
                 default: call_far_Ap();
@@ -333,8 +336,8 @@
             0x7: cmps_Yv_Xv();
         }
         0x15: decode OPCODE_OP_BOTTOM3 {
-            0x0: Inst::TEST(rAl,Ib);
-            0x1: Inst::TEST(rAX,Iz);
+            0x0: Inst::TEST(rAb,Ib);
+            0x1: Inst::TEST(rAv,Iz);
             0x2: stos_Yb_Al();
             0x3: stos_Yv_rAX();
             0x4: lods_Al_Xb();
@@ -343,8 +346,8 @@
             0x7: scas_Yv_rAX();
         }
         format Inst {
-            0x16: MOV(B,Ib);
-            0x17: MOV(B,Iv);
+            0x16: MOV(Bb,Ib);
+            0x17: MOV(Bv,Iv);
             0x18: decode OPCODE_OP_BOTTOM3 {
                 //0x0: group2_Eb_Ib();
                 0x0: decode MODRM_REG {
@@ -404,10 +407,55 @@
             0x7: iret();
         }
         0x1A: decode OPCODE_OP_BOTTOM3 {
-            0x0: group2_Eb_1();
-            0x1: group2_Ev_1();
-            0x2: group2_Eb_Cl();
-            0x3: group2_Ev_Cl();
+            format Inst {
+                //0x0: group2_Eb_1();
+                0x0: decode MODRM_REG {
+                    0x0: ROL_1(Eb);
+                    0x1: ROR_1(Eb);
+                    0x2: RCL_1(Eb);
+                    0x3: RCR_1(Eb);
+                    0x4: SAL_1(Eb);
+                    0x5: SHR_1(Eb);
+                    0x6: SAL_1(Eb);
+                    0x7: SAR_1(Eb);
+                }
+                //0x1: group2_Ev_1();
+                0x1: decode MODRM_REG {
+                    0x0: ROL_1(Ev);
+                    0x1: ROR_1(Ev);
+                    0x2: RCL_1(Ev);
+                    0x3: RCR_1(Ev);
+                    0x4: SAL_1(Ev);
+                    0x5: SHR_1(Ev);
+                    0x6: SAL_1(Ev);
+                    0x7: SAR_1(Ev);
+                }
+                //0x2: group2_Eb_Cl();
+                0x2: decode MODRM_REG {
+                    0x0: ROL(Eb,rCb);
+                    0x1: ROR(Eb,rCb);
+                    0x2: RCL(Eb,rCb);
+                    0x3: RCR(Eb,rCb);
+                    0x4: SAL(Eb,rCb);
+                    0x5: SHR(Eb,rCb);
+                    0x6: SAL(Eb,rCb);
+                    0x7: SAR(Eb,rCb);
+                }
+                //The second operand should have size "b", but to have
+                //consistent register sizes it's "v". This shouldn't have
+                //any affect on functionality.
+                //0x3: group2_Ev_Cl();
+                0x3: decode MODRM_REG {
+                    0x0: ROL(Ev,rCv);
+                    0x1: ROR(Ev,rCv);
+                    0x2: RCL(Ev,rCv);
+                    0x3: RCR(Ev,rCv);
+                    0x4: SAL(Ev,rCv);
+                    0x5: SHR(Ev,rCv);
+                    0x6: SAL(Ev,rCv);
+                    0x7: SAR(Ev,rCv);
+                }
+            }
             0x4: decode MODE_SUBMODE {
                 0x0: Inst::UD2();
                 default: aam_Ib();
@@ -465,8 +513,28 @@
                 {{"Tried to execute the rep/repe prefix!"}});
             0x4: hlt();
             0x5: cmc();
-            0x6: group3_Eb();
-            0x7: group3_Ev();
+            //0x6: group3_Eb();
+            0x6: decode MODRM_REG {
+                0x0: Inst::TEST(Eb,Iz);
+                0x1: Inst::TEST(Eb,Iz);
+                0x2: Inst::NOT(Eb);
+                0x3: Inst::NEG(Eb);
+                0x4: mul_Eb();
+                0x5: imul_Eb();
+                0x6: div_Eb();
+                0x7: idiv_Eb();
+            }
+            //0x7: group3_Ev();
+            0x7: decode MODRM_REG {
+                0x0: Inst::TEST(Ev,Iz);
+                0x1: Inst::TEST(Ev,Iz);
+                0x2: Inst::NOT(Ev);
+                0x3: Inst::NEG(Ev);
+                0x4: mul_Ev();
+                0x5: imul_Ev();
+                0x6: div_Ev();
+                0x7: idiv_Ev();
+            }
         }
         0x1F: decode OPCODE_OP_BOTTOM3 {
             0x0: clc();
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index e5631d37b..da4c82afa 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -81,21 +81,58 @@
                 0x0: invd();
                 0x1: wbinvd();
                 0x2: Inst::UD2();
-                0x3: UD2();
+                0x3: Inst::UD2();
                 0x4: Inst::UD2();
                 0x5: threednow();
                 0x6: threednow();
                 0x7: threednow();
             }
-            0x02: decode OPCODE_OP_BOTTOM3 {
-                0x0: holder();
-                0x1: holder();
-                0x2: holder();
-                0x3: holder();
-                0x4: holder();
-                0x5: holder();
-                0x6: holder();
-                0x7: holder();
+            0x02: decode LEGACY_DECODEVAL {
+                // no prefix
+                0x0: decode OPCODE_OP_BOTTOM3 {
+                    0x0: holder();
+                    0x1: holder();
+                    0x2: holder();
+                    0x3: holder();
+                    0x4: holder();
+                    0x5: holder();
+                    0x6: holder();
+                    0x7: holder();
+                }
+                // repe (0xF3)
+                0x4: decode OPCODE_OP_BOTTOM3 {
+                    0x0: holder();
+                    0x1: holder();
+                    0x2: holder();
+                    0x3: holder();
+                    0x4: holder();
+                    0x5: holder();
+                    0x6: holder();
+                    0x7: holder();
+                }
+                // operand size (0x66)
+                0x1: decode OPCODE_OP_BOTTOM3 {
+                    0x0: holder();
+                    0x1: holder();
+                    0x2: holder();
+                    0x3: holder();
+                    0x4: holder();
+                    0x5: holder();
+                    0x6: holder();
+                    0x7: holder();
+                }
+                // repne (0xF2)
+                0x8: decode OPCODE_OP_BOTTOM3 {
+                    0x0: holder();
+                    0x1: holder();
+                    0x2: holder();
+                    0x3: holder();
+                    0x4: holder();
+                    0x5: holder();
+                    0x6: holder();
+                    0x7: holder();
+                }
+                default: Inst::UD2();
             }
             0x03: decode OPCODE_OP_BOTTOM3 {
                 0x0: group17();
@@ -147,25 +184,27 @@
                 0x6: three_byte_opcode();
                 0x7: three_byte_opcode();
             }
-            0x08: decode OPCODE_OP_BOTTOM3 {
-                0x0: cmovo_Gv_Ev();
-                0x1: cmovno_Gv_Ev();
-                0x2: cmovb_Gv_Ev();
-                0x3: cmovnb_Gv_Ev();
-                0x4: cmovz_Gv_Ev();
-                0x5: cmovnz_Gv_Ev();
-                0x6: cmovbe_Gv_Ev();
-                0x7: cmovnbe_Gv_Ev();
-            }
-            0x09: decode OPCODE_OP_BOTTOM3 {
-                0x0: cmovs_Gv_Ev();
-                0x1: cmovns_Gv_Ev();
-                0x2: cmovp_Gv_Ev();
-                0x3: cmovnp_Gv_Ev();
-                0x4: cmovl_Gv_Ev();
-                0x5: cmovnl_Gv_Ev();
-                0x6: cmovle_Gv_Ev();
-                0x7: cmovnle_Gv_Ev();
+            format Inst {
+                0x08: decode OPCODE_OP_BOTTOM3 {
+                    0x0: CMOVO(Gv,Ev);
+                    0x1: CMOVNO(Gv,Ev);
+                    0x2: CMOVB(Gv,Ev);
+                    0x3: CMOVNB(Gv,Ev);
+                    0x4: CMOVZ(Gv,Ev);
+                    0x5: CMOVNZ(Gv,Ev);
+                    0x6: CMOVBE(Gv,Ev);
+                    0x7: CMOVNBE(Gv,Ev);
+                }
+                0x09: decode OPCODE_OP_BOTTOM3 {
+                    0x0: CMOVS(Gv,Ev);
+                    0x1: CMOVNS(Gv,Ev);
+                    0x2: CMOVP(Gv,Ev);
+                    0x3: CMOVNP(Gv,Ev);
+                    0x4: CMOVL(Gv,Ev);
+                    0x5: CMOVNL(Gv,Ev);
+                    0x6: CMOVLE(Gv,Ev);
+                    0x7: CMOVNLE(Gv,Ev);
+                }
             }
             0x0A: decode OPCODE_OP_BOTTOM3 {
                 0x0: holder();
@@ -248,26 +287,26 @@
                     0x6: JLE(Jz);
                     0x7: JNLE(Jz);
                 }
-            }
-            0x12: decode OPCODE_OP_BOTTOM3 {
-                0x0: seto_Eb();
-                0x1: setno_Eb();
-                0x2: setb_Eb();
-                0x3: setnb_Eb();
-                0x4: setz_Eb();
-                0x5: setnz_Eb();
-                0x6: setbe_Eb();
-                0x7: setnbe_Eb();
-            }
-            0x13: decode OPCODE_OP_BOTTOM3 {
-                0x0: sets_Eb();
-                0x1: setns_Eb();
-                0x2: setp_Eb();
-                0x3: setnp_Eb();
-                0x4: setl_Eb();
-                0x5: setnl_Eb();
-                0x6: setle_Eb();
-                0x7: setnle_Eb();
+                0x12: decode OPCODE_OP_BOTTOM3 {
+                    0x0: SETO(Eb);
+                    0x1: SETNO(Eb);
+                    0x2: SETB(Eb);
+                    0x3: SETNB(Eb);
+                    0x4: SETZ(Eb);
+                    0x5: SETNZ(Eb);
+                    0x6: SETBE(Eb);
+                    0x7: SETNBE(Eb);
+                }
+                0x13: decode OPCODE_OP_BOTTOM3 {
+                    0x0: SETS(Eb);
+                    0x1: SETNS(Eb);
+                    0x2: SETP(Eb);
+                    0x3: SETNP(Eb);
+                    0x4: SETL(Eb);
+                    0x5: SETNL(Eb);
+                    0x6: SETLE(Eb);
+                    0x7: SETNLE(Eb);
+                }
             }
             0x14: decode OPCODE_OP_BOTTOM3 {
                 0x0: push_fs();
@@ -296,8 +335,11 @@
                 0x3: btr_Ev_Gv();
                 0x4: lfs_Gz_Mp();
                 0x5: lgs_Gz_Mp();
-                0x6: Inst::MOVZX_B(Gv,Eb);
-                0x7: Inst::MOVZX_W(Gv,Ew);
+                //The size of the second operand in these instructions should
+                //really be "b" or "w", but it's set to v in order to have a
+                //consistent register size. This shouldn't affect behavior.
+                0x6: Inst::MOVZX_B(Gv,Ev);
+                0x7: Inst::MOVZX_W(Gv,Ev);
             }
             0x17: decode OPCODE_OP_BOTTOM3 {
                 0x0: jmpe_Jz(); // IA-64?
@@ -306,8 +348,11 @@
                 0x3: btc_Ev_Gv();
                 0x4: bsf_Gv_Ev();
                 0x5: bsr_Gv_Ev();
-                0x6: Inst::MOVSX_B(Gv,Eb);
-                0x7: Inst::MOVSX_W(Gv,Ew);
+                //The size of the second operand in these instructions should
+                //really be "b" or "w", but it's set to v in order to have a
+                //consistent register size. This shouldn't affect behavior.
+                0x6: Inst::MOVSX_B(Gv,Ev);
+                0x7: Inst::MOVSX_W(Gv,Ev);
             }
             0x18: decode OPCODE_OP_BOTTOM3 {
                 0x0: holder();
diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
index 05aa6cd69..7e5578a3c 100644
--- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
+++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
@@ -77,9 +77,9 @@ def macroop ADD_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     add t1, t1, t2
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADD_M_R
@@ -92,9 +92,9 @@ def macroop ADD_M_R
 def macroop ADD_P_R
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     add t1, t1, reg
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADD_R_M
@@ -106,7 +106,7 @@ def macroop ADD_R_M
 def macroop ADD_R_P
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     add reg, reg, t1
 };
 
@@ -130,7 +130,7 @@ def macroop SUB_R_M
 def macroop SUB_R_P
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sub reg, reg, t1
 };
 
@@ -146,9 +146,9 @@ def macroop SUB_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sub t1, t1, t2
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop SUB_M_R
@@ -161,9 +161,9 @@ def macroop SUB_M_R
 def macroop SUB_P_R
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sub t1, t1, reg
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADC_R_R
@@ -189,9 +189,9 @@ def macroop ADC_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     adc t1, t1, t2
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADC_M_R
@@ -204,9 +204,9 @@ def macroop ADC_M_R
 def macroop ADC_P_R
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     adc t1, t1, reg
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADC_R_M
@@ -218,7 +218,7 @@ def macroop ADC_R_M
 def macroop ADC_R_P
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     adc reg, reg, t1
 };
 
@@ -242,7 +242,7 @@ def macroop SBB_R_M
 def macroop SBB_R_P
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sbb reg, reg, t1
 };
 
@@ -258,9 +258,9 @@ def macroop SBB_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sbb t1, t1, t2
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop SBB_M_R
@@ -273,20 +273,28 @@ def macroop SBB_M_R
 def macroop SBB_P_R
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sbb t1, t1, reg
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop NEG_R
+{
+    sub reg, t0, reg, flags=(CF,OF,SF,ZF,AF,PF)
+};
+
+def macroop NEG_M
+{
+    ld t1, ds, [scale, index, base], disp
+    sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
     st t1, ds, [scale, index, base], disp
 };
+
+def macroop NEG_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
+    st t1, ds, [0, t0, t7], disp
+};
 '''
-#let {{
-#    class ADC(Inst):
-#	"Adc ^0 ^0 ^1"
-#    class ADD(Inst):
-#	"Add ^0 ^0 ^1"
-#    class SBB(Inst):
-#	"Sbb ^0 ^0 ^1"
-#    class SUB(Inst):
-#	"Sub ^0 ^0 ^1"
-#    class NEG(Inst):
-#	"Sub ^0 $0 ^0"
-#}};
diff --git a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
index eed39c10c..f53fa8f05 100644
--- a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
+++ b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
@@ -94,9 +94,3 @@ def macroop DEC_P
     st t1, ds, [0, t0, t7], disp
 };
 '''
-#let {{
-#    class DEC(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class INC(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
diff --git a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
index 8697bef65..339e18cf8 100644
--- a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
+++ b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
@@ -77,6 +77,27 @@ def macroop IMUL_R_P
     ld t1, ds, [scale, index, base], disp
     mul1s reg, reg, t1
 };
+
+def macroop IMUL_R_R_I
+{
+    limm t1, imm
+    mul1s reg, regm, t1
+};
+
+def macroop IMUL_R_M_I
+{
+    limm t1, imm
+    ld t2, ds, [scale, index, base], disp
+    mul1s reg, t2, t1
+};
+
+def macroop IMUL_R_P_I
+{
+    rdip t7
+    limm t1, imm
+    ld t2, ds, [0, t0, t7]
+    mul1s reg, t2, t1
+};
 '''
 #let {{
 #    class MUL(Inst):
diff --git a/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py b/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py
index 3d9250c2d..2008bf666 100644
--- a/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py
+++ b/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py
@@ -53,8 +53,340 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
-#let {{
-#    class SETcc(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop SETZ_R
+{
+    movi reg, reg, 1, flags=(CZF,)
+    movi reg, reg, 0, flags=(nCZF,)
+};
+
+def macroop SETZ_M
+{
+    movi t1, t1, 1, flags=(CZF,)
+    movi t1, t1, 0, flags=(nCZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETZ_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CZF,)
+    movi t1, t1, 0, flags=(nCZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNZ_R
+{
+    movi reg, reg, 1, flags=(nCZF,)
+    movi reg, reg, 0, flags=(CZF,)
+};
+
+def macroop SETNZ_M
+{
+    movi t1, t1, 1, flags=(nCZF,)
+    movi t1, t1, 0, flags=(CZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNZ_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCZF,)
+    movi t1, t1, 0, flags=(CZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETB_R
+{
+    movi reg, reg, 1, flags=(CCF,)
+    movi reg, reg, 0, flags=(nCCF,)
+};
+
+def macroop SETB_M
+{
+    movi t1, t1, 1, flags=(CCF,)
+    movi t1, t1, 0, flags=(nCCF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETB_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CCF,)
+    movi t1, t1, 0, flags=(nCCF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNB_R
+{
+    movi reg, reg, 1, flags=(nCCF,)
+    movi reg, reg, 0, flags=(CCF,)
+};
+
+def macroop SETNB_M
+{
+    movi t1, t1, 1, flags=(nCCF,)
+    movi t1, t1, 0, flags=(CCF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNB_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCCF,)
+    movi t1, t1, 0, flags=(CCF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETBE_R
+{
+    movi reg, reg, 1, flags=(CCvZF,)
+    movi reg, reg, 0, flags=(nCCvZF,)
+};
+
+def macroop SETBE_M
+{
+    movi t1, t1, 1, flags=(CCvZF,)
+    movi t1, t1, 0, flags=(nCCvZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETBE_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CCvZF,)
+    movi t1, t1, 0, flags=(nCCvZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNBE_R
+{
+    movi reg, reg, 1, flags=(nCCvZF,)
+    movi reg, reg, 0, flags=(CCvZF,)
+};
+
+def macroop SETNBE_M
+{
+    movi t1, t1, 1, flags=(nCCvZF,)
+    movi t1, t1, 0, flags=(CCvZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNBE_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCCvZF,)
+    movi t1, t1, 0, flags=(CCvZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETS_R
+{
+    movi reg, reg, 1, flags=(CSF,)
+    movi reg, reg, 0, flags=(nCSF,)
+};
+
+def macroop SETS_M
+{
+    movi t1, t1, 1, flags=(CSF,)
+    movi t1, t1, 0, flags=(nCSF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETS_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CSF,)
+    movi t1, t1, 0, flags=(nCSF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNS_R
+{
+    movi reg, reg, 1, flags=(nCSF,)
+    movi reg, reg, 0, flags=(CSF,)
+};
+
+def macroop SETNS_M
+{
+    movi t1, t1, 1, flags=(nCSF,)
+    movi t1, t1, 0, flags=(CSF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNS_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCSF,)
+    movi t1, t1, 0, flags=(CSF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETP_R
+{
+    movi reg, reg, 1, flags=(CPF,)
+    movi reg, reg, 0, flags=(nCPF,)
+};
+
+def macroop SETP_M
+{
+    movi t1, t1, 1, flags=(CPF,)
+    movi t1, t1, 0, flags=(nCPF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETP_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CPF,)
+    movi t1, t1, 0, flags=(nCPF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNP_R
+{
+    movi reg, reg, 1, flags=(nCPF,)
+    movi reg, reg, 0, flags=(CPF,)
+};
+
+def macroop SETNP_M
+{
+    movi t1, t1, 1, flags=(nCPF,)
+    movi t1, t1, 0, flags=(CPF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNP_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCPF,)
+    movi t1, t1, 0, flags=(CPF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETL_R
+{
+    movi reg, reg, 1, flags=(CSxOF,)
+    movi reg, reg, 0, flags=(nCSxOF,)
+};
+
+def macroop SETL_M
+{
+    movi t1, t1, 1, flags=(CSxOF,)
+    movi t1, t1, 0, flags=(nCSxOF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETL_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CSxOF,)
+    movi t1, t1, 0, flags=(nCSxOF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNL_R
+{
+    movi reg, reg, 1, flags=(nCSxOF,)
+    movi reg, reg, 0, flags=(CSxOF,)
+};
+
+def macroop SETNL_M
+{
+    movi t1, t1, 1, flags=(nCSxOF,)
+    movi t1, t1, 0, flags=(CSxOF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNL_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCSxOF,)
+    movi t1, t1, 0, flags=(CSxOF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETLE_R
+{
+    movi reg, reg, 1, flags=(CSxOvZF,)
+    movi reg, reg, 0, flags=(nCSxOvZF,)
+};
+
+def macroop SETLE_M
+{
+    movi t1, t1, 1, flags=(CSxOvZF,)
+    movi t1, t1, 0, flags=(nCSxOvZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETLE_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CSxOvZF,)
+    movi t1, t1, 0, flags=(nCSxOvZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNLE_R
+{
+    movi reg, reg, 1, flags=(nCSxOvZF,)
+    movi reg, reg, 0, flags=(CSxOvZF,)
+};
+
+def macroop SETNLE_M
+{
+    movi t1, t1, 1, flags=(nCSxOvZF,)
+    movi t1, t1, 0, flags=(CSxOvZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNLE_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCSxOvZF,)
+    movi t1, t1, 0, flags=(CSxOvZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETO_R
+{
+    movi reg, reg, 1, flags=(COF,)
+    movi reg, reg, 0, flags=(nCOF,)
+};
+
+def macroop SETO_M
+{
+    movi t1, t1, 1, flags=(COF,)
+    movi t1, t1, 0, flags=(nCOF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETO_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(COF,)
+    movi t1, t1, 0, flags=(nCOF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNO_R
+{
+    movi reg, reg, 1, flags=(nCOF,)
+    movi reg, reg, 0, flags=(COF,)
+};
+
+def macroop SETNO_M
+{
+    movi t1, t1, 1, flags=(nCOF,)
+    movi t1, t1, 0, flags=(COF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNO_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCOF,)
+    movi t1, t1, 0, flags=(COF,)
+    st t1, ds, [0, t0, t7], disp
+};
+'''
diff --git a/src/arch/x86/isa/insts/data_conversion/sign_extension.py b/src/arch/x86/isa/insts/data_conversion/sign_extension.py
index e96eee694..6a2612c3c 100644
--- a/src/arch/x86/isa/insts/data_conversion/sign_extension.py
+++ b/src/arch/x86/isa/insts/data_conversion/sign_extension.py
@@ -53,7 +53,18 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
+microcode = '''
+def macroop CDQE_R {
+    sext reg, reg, "env.dataSize << 2"
+};
+
+def macroop CQO_R_R {
+    # A shift might be slower than, for example, an explicit sign extension,
+    # so it might be worthwhile to try to find an alternative.
+    mov regm, regm, reg
+    sra regm, regm, "env.dataSize * 8 - 1"
+};
+'''
 #let {{
 #    class CBW(Inst):
 #	"GenFault ${new UnimpInstFault}"
diff --git a/src/arch/x86/isa/insts/data_transfer/conditional_move.py b/src/arch/x86/isa/insts/data_transfer/conditional_move.py
index 513e90c4e..17f8841f2 100644
--- a/src/arch/x86/isa/insts/data_transfer/conditional_move.py
+++ b/src/arch/x86/isa/insts/data_transfer/conditional_move.py
@@ -53,8 +53,292 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
-#let {{
-#    class CMOVcc(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop CMOVZ_R_R
+{
+    mov reg, reg, regm, flags=(CZF,)
+};
+
+def macroop CMOVZ_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CZF,)
+};
+
+def macroop CMOVZ_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CZF,)
+};
+
+def macroop CMOVNZ_R_R
+{
+    mov reg, reg, regm, flags=(nCZF,)
+};
+
+def macroop CMOVNZ_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCZF,)
+};
+
+def macroop CMOVNZ_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCZF,)
+};
+
+def macroop CMOVB_R_R
+{
+    mov reg, reg, regm, flags=(CCF,)
+};
+
+def macroop CMOVB_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CCF,)
+};
+
+def macroop CMOVB_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CCF,)
+};
+
+def macroop CMOVNB_R_R
+{
+    mov reg, reg, regm, flags=(nCCF,)
+};
+
+def macroop CMOVNB_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCCF,)
+};
+
+def macroop CMOVNB_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCCF,)
+};
+
+def macroop CMOVBE_R_R
+{
+    mov reg, reg, regm, flags=(CCvZF,)
+};
+
+def macroop CMOVBE_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CCvZF,)
+};
+
+def macroop CMOVBE_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CCvZF,)
+};
+
+def macroop CMOVNBE_R_R
+{
+    mov reg, reg, regm, flags=(nCCvZF,)
+};
+
+def macroop CMOVNBE_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCCvZF,)
+};
+
+def macroop CMOVNBE_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCCvZF,)
+};
+
+def macroop CMOVS_R_R
+{
+    mov reg, reg, regm, flags=(CSF,)
+};
+
+def macroop CMOVS_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CSF,)
+};
+
+def macroop CMOVS_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CSF,)
+};
+
+def macroop CMOVNS_R_R
+{
+    mov reg, reg, regm, flags=(nCSF,)
+};
+
+def macroop CMOVNS_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCSF,)
+};
+
+def macroop CMOVNS_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCSF,)
+};
+
+def macroop CMOVP_R_R
+{
+    mov reg, reg, regm, flags=(CPF,)
+};
+
+def macroop CMOVP_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CPF,)
+};
+
+def macroop CMOVP_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CPF,)
+};
+
+def macroop CMOVNP_R_R
+{
+    mov reg, reg, regm, flags=(nCPF,)
+};
+
+def macroop CMOVNP_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, regm, flags=(nCPF,)
+};
+
+def macroop CMOVNP_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, regm, flags=(nCPF,)
+};
+
+def macroop CMOVL_R_R
+{
+    mov reg, reg, regm, flags=(CSxOF,)
+};
+
+def macroop CMOVL_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CSxOF,)
+};
+
+def macroop CMOVL_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CSxOF,)
+};
+
+def macroop CMOVNL_R_R
+{
+    mov reg, reg, regm, flags=(nCSxOF,)
+};
+
+def macroop CMOVNL_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCSxOF,)
+};
+
+def macroop CMOVNL_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCSxOF,)
+};
+
+def macroop CMOVLE_R_R
+{
+    mov reg, reg, regm, flags=(CSxOvZF,)
+};
+
+def macroop CMOVLE_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CSxOvZF,)
+};
+
+def macroop CMOVLE_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CSxOvZF,)
+};
+
+def macroop CMOVNLE_R_R
+{
+    mov reg, reg, regm, flags=(nCSxOvZF,)
+};
+
+def macroop CMOVNLE_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCSxOvZF,)
+};
+
+def macroop CMOVNLE_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCSxOvZF,)
+};
+
+def macroop CMOVO_R_R
+{
+    mov reg, reg, regm, flags=(COF,)
+};
+
+def macroop CMOVO_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(COF,)
+};
+
+def macroop CMOVO_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(COF,)
+};
+
+def macroop CMOVNO_R_R
+{
+    mov reg, reg, regm, flags=(nCOF,)
+};
+
+def macroop CMOVNO_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCOF,)
+};
+
+def macroop CMOVNO_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCOF,)
+};
+'''
diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
index c381dc4f4..889e7b88b 100644
--- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
@@ -62,6 +62,25 @@ def macroop POP_R {
     addi rsp, rsp, dsz
 };
 
+def macroop POP_M {
+    # Make the default data size of pops 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    ld t1, ss, [0, t0, rsp]
+    addi rsp, rsp, dsz
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop POP_P {
+    # Make the default data size of pops 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    rdip t7
+    ld t1, ss, [0, t0, rsp]
+    addi rsp, rsp, dsz
+    st t1, ds, [0, t0, t7]
+};
+
 def macroop PUSH_R {
     # Make the default data size of pops 64 bits in 64 bit mode
     .adjust_env oszIn64Override
@@ -70,6 +89,15 @@ def macroop PUSH_R {
     st reg, ss, [0, t0, rsp]
 };
 
+def macroop PUSH_I {
+    # Make the default data size of pops 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    limm t1, imm
+    subi rsp, rsp, dsz
+    st t1, ss, [0, t0, rsp]
+};
+
 def macroop PUSH_M {
     # Make the default data size of pops 64 bits in 64 bit mode
     .adjust_env oszIn64Override
@@ -88,16 +116,32 @@ def macroop PUSH_P {
     subi rsp, rsp, dsz
     st t1, ss, [0, t0, rsp]
 };
+
+def macroop PUSHA {
+    st rax, ss, [0, t0, rsp], "-0 * env.dataSize"
+    st rcx, ss, [0, t0, rsp], "-1 * env.dataSize"
+    st rdx, ss, [0, t0, rsp], "-2 * env.dataSize"
+    st rbx, ss, [0, t0, rsp], "-3 * env.dataSize"
+    st rsp, ss, [0, t0, rsp], "-4 * env.dataSize"
+    st rbp, ss, [0, t0, rsp], "-5 * env.dataSize"
+    st rsi, ss, [0, t0, rsp], "-6 * env.dataSize"
+    st rdi, ss, [0, t0, rsp], "-7 * env.dataSize"
+    subi rsp, rsp, "8 * env.dataSize"
+};
+
+def macroop POPA {
+    st rdi, ss, [0, t0, rsp], "0 * env.dataSize"
+    st rsi, ss, [0, t0, rsp], "1 * env.dataSize"
+    st rbp, ss, [0, t0, rsp], "2 * env.dataSize"
+    st rsp, ss, [0, t0, rsp], "3 * env.dataSize"
+    st rbx, ss, [0, t0, rsp], "4 * env.dataSize"
+    st rdx, ss, [0, t0, rsp], "5 * env.dataSize"
+    st rcx, ss, [0, t0, rsp], "6 * env.dataSize"
+    st rax, ss, [0, t0, rsp], "7 * env.dataSize"
+    addi rsp, rsp, "8 * env.dataSize"
+};
 '''
 #let {{
-#    class POPA(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class POPAD(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class PUSHA(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class PUSHAD(Inst):
-#	"GenFault ${new UnimpInstFault}"
 #    class ENTER(Inst):
 #	"GenFault ${new UnimpInstFault}"
 #    class LEAVE(Inst):
diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py
index f99638cac..bbc15f8fa 100644
--- a/src/arch/x86/isa/insts/logical.py
+++ b/src/arch/x86/isa/insts/logical.py
@@ -221,16 +221,27 @@ def macroop AND_P_R
     and t1, t1, reg
     st t1, ds, [scale, index, base], disp
 };
+
+def macroop NOT_R
+{
+    limm t1, -1
+    xor reg, reg, t1
+};
+
+def macroop NOT_M
+{
+    limm t1, -1
+    ld t2, ds, [scale, index, base], disp
+    xor t2, t2, t1
+    st t2, ds, [scale, index, base], disp
+};
+
+def macroop NOT_P
+{
+    limm t1, -1
+    rdip t7
+    ld t2, ds, [0, t0, t7], disp
+    xor t2, t2, t1
+    st t2, ds, [0, t0, t7], disp
+};
 '''
-#let {{
-#microcodeString = '''
-#    def macroop OR
-#    {
-#	Or reg reg regm
-#    };
-#    def macroop NOT
-#    {
-#	Xor reg reg "0xFFFFFFFFFFFFFFFFULL"
-#    };
-#'''
-#}};
diff --git a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py
index 0988f8815..538e641ab 100644
--- a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py
+++ b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py
@@ -56,13 +56,13 @@
 microcode = '''
 def macroop ROL_R_I
 {
-    rol reg, reg, imm
+    roli reg, reg, imm
 };
 
 def macroop ROL_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    rol t1, t1, imm
+    roli t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -70,19 +70,59 @@ def macroop ROL_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    rol t1, t1, imm
+    roli t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop ROL_1_R
+{
+    roli reg, reg, 1
+};
+
+def macroop ROL_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    roli t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ROL_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    roli t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop ROL_R_R
+{
+    rol reg, reg, regm
+};
+
+def macroop ROL_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    rol t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ROL_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rol t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ROR_R_I
 {
-    ror reg, reg, imm
+    rori reg, reg, imm
 };
 
 def macroop ROR_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    ror t1, t1, imm
+    rori t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -90,19 +130,59 @@ def macroop ROR_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    ror t1, t1, imm
+    rori t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop ROR_1_R
+{
+    rori reg, reg, 1
+};
+
+def macroop ROR_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    rori t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ROR_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rori t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop ROR_R_R
+{
+    ror reg, reg, regm
+};
+
+def macroop ROR_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    ror t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ROR_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    ror t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop RCL_R_I
 {
-    rcl reg, reg, imm
+    rcli reg, reg, imm
 };
 
 def macroop RCL_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    rcl t1, t1, imm
+    rcli t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -110,19 +190,59 @@ def macroop RCL_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    rcl t1, t1, imm
+    rcli t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop RCL_1_R
+{
+    rcli reg, reg, 1
+};
+
+def macroop RCL_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    rcli t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop RCL_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rcli t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop RCL_R_R
+{
+    rcl reg, reg, regm
+};
+
+def macroop RCL_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    rcl t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop RCL_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rcl t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop RCR_R_I
 {
-    rcr reg, reg, imm
+    rcri reg, reg, imm
 };
 
 def macroop RCR_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    rcr t1, t1, imm
+    rcri t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -130,13 +250,47 @@ def macroop RCR_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    rcr t1, t1, imm
+    rcri t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop RCR_1_R
+{
+    rcri reg, reg, 1
+};
+
+def macroop RCR_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    rcri t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop RCR_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rcri t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop RCR_R_R
+{
+    rcr reg, reg, regm
+};
+
+def macroop RCR_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    rcr t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop RCR_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rcr t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 '''
-#let {{
-#    class RCL(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class RCR(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
diff --git a/src/arch/x86/isa/insts/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/rotate_and_shift/shift.py
index 5a04317d9..64eab3edc 100644
--- a/src/arch/x86/isa/insts/rotate_and_shift/shift.py
+++ b/src/arch/x86/isa/insts/rotate_and_shift/shift.py
@@ -56,13 +56,13 @@
 microcode = '''
 def macroop SAL_R_I
 {
-    sll reg, reg, imm
+    slli reg, reg, imm
 };
 
 def macroop SAL_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    sll t1, t1, imm
+    slli t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -70,19 +70,59 @@ def macroop SAL_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    sll t1, t1, imm
+    slli t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SAL_1_R
+{
+    slli reg, reg, 1
+};
+
+def macroop SAL_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    slli t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SAL_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    slli t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SAL_R_R
+{
+    sll reg, reg, regm
+};
+
+def macroop SAL_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    sll t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SAL_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    sll t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop SHR_R_I
 {
-    srl reg, reg, imm
+    srli reg, reg, imm
 };
 
 def macroop SHR_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    srl t1, t1, imm
+    srli t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -90,19 +130,59 @@ def macroop SHR_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    srl t1, t1, imm
+    srli t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SHR_1_R
+{
+    srli reg, reg, 1
+};
+
+def macroop SHR_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    srli t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SHR_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    srli t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SHR_R_R
+{
+    srl reg, reg, regm
+};
+
+def macroop SHR_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    srl t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SHR_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    srl t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop SAR_R_I
 {
-    sra reg, reg, imm
+    srai reg, reg, imm
 };
 
 def macroop SAR_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    sra t1, t1, imm
+    srai t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -110,21 +190,47 @@ def macroop SAR_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    sra t1, t1, imm
+    srai t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SAR_1_R
+{
+    srai reg, reg, 1
+};
+
+def macroop SAR_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    srai t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SAR_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    srai t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SAR_R_R
+{
+    sra reg, reg, regm
+};
+
+def macroop SAR_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    sra t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SAR_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    sra t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 '''
-#let {{
-#    class SAL(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SAR(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SHL(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SHR(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SHLD(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SHRD(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa
index 8453a4fe9..4131246a4 100644
--- a/src/arch/x86/isa/macroop.isa
+++ b/src/arch/x86/isa/macroop.isa
@@ -196,18 +196,34 @@ let {{
             self.regUsed = False
             self.regm = "0"
             self.regmUsed = False
+            self.size = None
             self.addressSize = "ADDRSIZE"
             self.dataSize = "OPSIZE"
             self.stackSize = "STACKSIZE"
             self.doModRM = False
 
         def getAllocator(self):
+            if self.size == 'b':
+                self.dataSize = 1
+            elif self.size == 'd':
+                self.dataSize = 4
+            elif self.size == 'q':
+                self.dataSize = 8
+            elif self.size == 'v':
+                self.dataSize = "OPSIZE"
+            elif self.size == 'w':
+                self.dataSize = 2
+            elif self.size == 'z':
+                self.dataSize = "((OPSIZE == 8) ? 4 : OPSIZE)"
+            elif self.size:
+                raise Exception, "Unrecognized size type %s!" % self.size
             return '''EmulEnv(%(reg)s,
                               %(regm)s,
                               %(dataSize)s,
                               %(addressSize)s,
                               %(stackSize)s)''' % \
                 self.__dict__
+
         def addReg(self, reg):
             if not self.regUsed:
                 self.reg = reg
@@ -217,6 +233,13 @@ let {{
                 self.regmUsed = True
             else:
                 raise Exception, "EmulEnv is out of register specialization spots."
+        def setSize(self, size):
+            if not self.size:
+                self.size = size
+            else:
+                if self.size is not size:
+                    raise Exception, "Conflicting register sizes %s and %s!" %\
+                        (self.size, size)
 }};
 
 let {{
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index ccf519963..18cbc6082 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -123,24 +123,9 @@ def template MicroLoadExecute {{
         %(ea_code)s;
         DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
 
-        unsigned flags = 0;
-        switch(dataSize)
-        {
-          case 1:
-            fault = xc->read(EA, (uint8_t&)Mem, flags);
-            break;
-          case 2:
-            fault = xc->read(EA, (uint16_t&)Mem, flags);
-            break;
-          case 4:
-            fault = xc->read(EA, (uint32_t&)Mem, flags);
-            break;
-          case 8:
-            fault = xc->read(EA, (uint64_t&)Mem, flags);
-            break;
-          default:
-            panic("Bad operand size!\n");
-        }
+        fault = read(xc, EA, Mem, 0);
+        int offset = EA & (dataSize - 1);
+        Mem = bits(Mem, (offset + dataSize) * 8 - 1,  offset * 8);
 
         if(fault == NoFault)
         {
@@ -167,24 +152,8 @@ def template MicroLoadInitiateAcc {{
         %(ea_code)s;
         DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
 
-        unsigned flags = 0;
-        switch(dataSize)
-        {
-          case 1:
-            fault = xc->read(EA, (uint8_t&)Mem, flags);
-            break;
-          case 2:
-            fault = xc->read(EA, (uint16_t&)Mem, flags);
-            break;
-          case 4:
-            fault = xc->read(EA, (uint32_t&)Mem, flags);
-            break;
-          case 8:
-            fault = xc->read(EA, (uint64_t&)Mem, flags);
-            break;
-          default:
-            panic("Bad operand size!\n");
-        }
+        int offset = EA & (dataSize - 1);
+        fault = read(xc, EA, Mem, offset);
 
         return fault;
     }
@@ -201,6 +170,8 @@ def template MicroLoadCompleteAcc {{
         %(op_rd)s;
 
         Mem = pkt->get<typeof(Mem)>();
+        int offset = pkt->flags;
+        Mem = bits(Mem, (offset + dataSize) * 8 - 1,  offset * 8);
         %(code)s;
 
         if(fault == NoFault)
@@ -230,30 +201,13 @@ def template MicroStoreExecute {{
 
         if(fault == NoFault)
         {
-            unsigned flags = 0;
-            uint64_t *res = 0;
-            switch(dataSize)
+            Mem = Mem << ((EA & (dataSize - 1)) * 8);
+            fault = write(xc, Mem, EA, 0);
+            if(fault == NoFault)
             {
-              case 1:
-                fault = xc->write((uint8_t&)Mem, EA, flags, res);
-                break;
-              case 2:
-                fault = xc->write((uint16_t&)Mem, EA, flags, res);
-                break;
-              case 4:
-                fault = xc->write((uint32_t&)Mem, EA, flags, res);
-                break;
-              case 8:
-                fault = xc->write((uint64_t&)Mem, EA, flags, res);
-                break;
-              default:
-                panic("Bad operand size!\n");
+                %(op_wb)s;
             }
         }
-        if(fault == NoFault)
-        {
-            %(op_wb)s;
-        }
 
         return fault;
     }
@@ -275,30 +229,13 @@ def template MicroStoreInitiateAcc {{
 
         if(fault == NoFault)
         {
-            unsigned flags = 0;
-            uint64_t *res = 0;
-            switch(dataSize)
+            Mem = Mem << ((EA & (dataSize - 1)) * 8);
+            fault = write(xc, Mem, EA, 0);
+            if(fault == NoFault)
             {
-              case 1:
-                fault = xc->write((uint8_t&)Mem, EA, flags, res);
-                break;
-              case 2:
-                fault = xc->write((uint16_t&)Mem, EA, flags, res);
-                break;
-              case 4:
-                fault = xc->write((uint32_t&)Mem, EA, flags, res);
-                break;
-              case 8:
-                fault = xc->write((uint64_t&)Mem, EA, flags, res);
-                break;
-              default:
-                panic("Bad operand size!\n");
+                %(op_wb)s;
             }
         }
-        if(fault == NoFault)
-        {
-            %(op_wb)s;
-        }
         return fault;
     }
 }};
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index dbbe11c90..bb34df7df 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -343,7 +343,7 @@ let {{
         immCode = matcher.sub("imm8", code)
 
         if subtract:
-            secondSrc = "-op2, true"
+            secondSrc = "~op2, true"
         else:
             secondSrc = "op2"
 
@@ -466,11 +466,11 @@ let {{
 
     # Shift instructions
     defineMicroRegOp('Sll', '''
-            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
             DestReg = merge(DestReg, SrcReg1 << shiftAmt, dataSize);
             ''')
     defineMicroRegOp('Srl', '''
-            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
             // Because what happens to the bits shift -in- on a right shift
             // is not defined in the C/C++ standard, we have to mask them out
             // to be sure they're zero.
@@ -478,7 +478,7 @@ let {{
             DestReg = merge(DestReg, (SrcReg1 >> shiftAmt) & logicalMask, dataSize);
             ''')
     defineMicroRegOp('Sra', '''
-            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
             // Because what happens to the bits shift -in- on a right shift
             // is not defined in the C/C++ standard, we have to sign extend
             // them manually to be sure.
@@ -488,7 +488,7 @@ let {{
             ''')
     defineMicroRegOp('Ror', '''
             uint8_t shiftAmt =
-                (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
             if(shiftAmt)
             {
                 uint64_t top = SrcReg1 << (dataSize * 8 - shiftAmt);
@@ -500,7 +500,7 @@ let {{
             ''')
     defineMicroRegOp('Rcr', '''
             uint8_t shiftAmt =
-                (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
             if(shiftAmt)
             {
                 CCFlagBits flags = ccFlagBits;
@@ -515,7 +515,7 @@ let {{
             ''')
     defineMicroRegOp('Rol', '''
             uint8_t shiftAmt =
-                (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
             if(shiftAmt)
             {
                 uint64_t top = SrcReg1 << shiftAmt;
@@ -528,7 +528,7 @@ let {{
             ''')
     defineMicroRegOp('Rcl', '''
             uint8_t shiftAmt =
-                (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
             if(shiftAmt)
             {
                 CCFlagBits flags = ccFlagBits;
diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa
index 5165ea206..a45c6e80f 100644
--- a/src/arch/x86/isa/specialize.isa
+++ b/src/arch/x86/isa/specialize.isa
@@ -114,7 +114,8 @@ let {{
             self.reg = match.group("reg")
             self.tag = match.group("tag")
             self.size = match.group("size")
-            self.rsize = match.group("rsize")
+            if not self.size:
+                self.size = match.group("rsize")
 
     ModRMRegIndex = "(MODRM_REG | (REX_R << 3))"
     ModRMRMIndex = "(MODRM_RM | (REX_B << 3))"
@@ -129,6 +130,10 @@ let {{
             opType = OpType(opTypes[0])
             opTypes.pop(0)
 
+            if opType.tag not in ("I", "J"):
+                if opType.size:
+                    env.setSize(opType.size)
+
             if opType.reg:
                 #Figure out what to do with fixed register operands
                 #This is the index to use, so we should stick it some place.
@@ -136,13 +141,6 @@ let {{
                     env.addReg("INTREG_R%sX | (REX_B << 3)" % opType.reg)
                 else:
                     env.addReg("INTREG_R%s | (REX_B << 3)" % opType.reg)
-                if opType.size:
-                    if opType.rsize in ("l", "h", "b"):
-                        print "byte"
-                    elif opType.rsize == "x":
-                        print "word"
-                    else:
-                        print "Didn't recognize fixed register size %s!" % opType.rsize
                 Name += "_R"
             elif opType.tag == "B":
                 # This refers to registers whose index is encoded as part of the opcode