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authorGabe Black <gblack@eecs.umich.edu>2007-08-29 20:36:12 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-08-29 20:36:12 -0700
commit22830c074707c2998916f77d12cb69b929e9c1ab (patch)
tree4b8bebf3424db66e58c47f8d317ecdc96b3fb744 /src/arch/x86/isa
parent34f3c9d196cdabbc1f1fd02a6052c86c5a1c12e9 (diff)
downloadgem5-22830c074707c2998916f77d12cb69b929e9c1ab.tar.xz
X86: Add load and store microops that use the fp registers.
--HG-- extra : convert_revision : 153a055e888d8c47d59758a599dbd38f63008137
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/microops/ldstop.isa2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index c979ace04..1bdc1d37a 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -386,6 +386,7 @@ let {{
microopClasses[name] = LoadOp
defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);')
+ defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;')
def defineMicroStoreOp(mnemonic, code):
global header_output
@@ -415,6 +416,7 @@ let {{
microopClasses[name] = StoreOp
defineMicroStoreOp('St', 'Mem = Data;')
+ defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;')
iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
{"code": "Data = merge(Data, EA, dataSize);", "ea_code": calculateEA})