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authorGabe Black <gblack@eecs.umich.edu>2007-08-29 20:36:44 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-08-29 20:36:44 -0700
commit3b97b6e0e25ebf33507dcd68cd9d21096df50cda (patch)
treef84ed4d17db4470b52ebdeea75f7b2e99e27f9c5 /src/arch/x86/isa
parent22830c074707c2998916f77d12cb69b929e9c1ab (diff)
downloadgem5-3b97b6e0e25ebf33507dcd68cd9d21096df50cda.tar.xz
X86: Add an fp move microop.
--HG-- extra : convert_revision : a9d6d3568cd2c6a65df91bf56ee1e43523f04630
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/microops/regop.isa36
1 files changed, 21 insertions, 15 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 616f7a5fc..cacdc7144 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -357,7 +357,7 @@ let {{
# This creates a python representations of a microop which are a cross
# product of reg/immediate and flag/no flag versions.
def defineMicroRegOp(mnemonic, code, flagCode=genCCFlagBits, \
- cc=False, elseCode=";"):
+ cc=False, doImm=True, elseCode=";"):
Name = mnemonic
name = mnemonic.lower()
@@ -392,21 +392,22 @@ let {{
regCode, flagCode=regFlagCode,
condCheck=condCode, elseCode=elseCode);
- class RegOpChildImm(RegOpImm):
- mnemonic = name + 'i'
- className = Name + 'Imm'
- def __init__(self, dest, src1, src2, \
- flags=None, dataSize="env.dataSize"):
- super(RegOpChildImm, self).__init__(dest, src1, src2, \
- flags, dataSize)
+ if doImm:
+ class RegOpChildImm(RegOpImm):
+ mnemonic = name + 'i'
+ className = Name + 'Imm'
+ def __init__(self, dest, src1, src2, \
+ flags=None, dataSize="env.dataSize"):
+ super(RegOpChildImm, self).__init__(dest, src1, src2, \
+ flags, dataSize)
- microopClasses[name + 'i'] = RegOpChildImm
+ microopClasses[name + 'i'] = RegOpChildImm
- setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
- immCode, imm=True);
- setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm",
- immCode, flagCode=immFlagCode,
- condCheck=condCode, elseCode=elseCode, imm=True);
+ setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
+ immCode, imm=True);
+ setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm",
+ immCode, flagCode=immFlagCode,
+ condCheck=condCode, elseCode=elseCode, imm=True);
# This has it's own function because Wr ops have implicit destinations
def defineMicroRegOpWr(mnemonic, code, elseCode=";"):
@@ -562,9 +563,14 @@ let {{
#
# HACK HACK HACK HACK - Put psrc1 in here but make it inert to shut up gcc.
#
- defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, psrc1 * 0 + op2, dataSize)',
+ defineMicroRegOp('Mov',
+ 'DestReg = merge(SrcReg1, psrc1 * 0 + op2, dataSize)',
elseCode='DestReg=DestReg;', cc=True)
+ defineMicroRegOp('Movfp',
+ 'FpDestReg = FpSrcReg2 + psrc1 * 0 + psrc2 * 0',
+ elseCode='FpDestReg=FpDestReg;', cc=True, doImm=False)
+
# Shift instructions
defineMicroRegOp('Sll', '''
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));