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authorGabe Black <gblack@eecs.umich.edu>2007-11-13 01:31:43 -0800
committerGabe Black <gblack@eecs.umich.edu>2007-11-13 01:31:43 -0800
commit5772e3cadaf12cf155e6ad0cb79a3b7333d1dd10 (patch)
tree319cf1613ae6f9a6a435d5f269ea3a9361a2068e /src/arch/x86/isa
parent1048b548fabfb7af2113f226f2151d3eb0e63289 (diff)
downloadgem5-5772e3cadaf12cf155e6ad0cb79a3b7333d1dd10.tar.xz
X86: Make microcode use presegmentation RIPs and the rest of m5 use post segmentation RIPS.
--HG-- extra : convert_revision : d8cda7c8b9a2afb8a9d601b6d61529a96c5f87fe
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/microops/regop.isa4
-rw-r--r--src/arch/x86/isa/operands.isa1
2 files changed, 3 insertions, 2 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 58b267e0d..4ac3a9d98 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -835,7 +835,7 @@ let {{
'''
class Wrip(WrRegOp, CondRegOp):
- code = 'RIP = psrc1 + sop2'
+ code = 'RIP = psrc1 + sop2 + CSBase'
else_code="RIP = RIP;"
class Br(WrRegOp, CondRegOp):
@@ -846,7 +846,7 @@ let {{
code = 'ccFlagBits = psrc1 ^ op2'
class Rdip(RdRegOp):
- code = 'DestReg = RIP'
+ code = 'DestReg = RIP - CSBase'
class Ruflags(RdRegOp):
code = 'DestReg = ccFlagBits'
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 542638edd..f50e71727 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -126,5 +126,6 @@ def operands {{
'ControlSrc1': ('ControlReg', 'uqw', 'MISCREG_CR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 72),
'EferOp': ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 73),
'CR4Op': ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 74),
+ 'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
}};