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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-29 20:34:52 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-29 20:34:52 -0700 |
| commit | bc3635a110747123be066de5238961938ea5df78 (patch) | |
| tree | d9a4ac053ec78afd29a90f2ad9b82b0b18829a20 /src/arch/x86/isa | |
| parent | 6204d00940ecae631b040f2b6f46a11eb58cebb6 (diff) | |
| download | gem5-bc3635a110747123be066de5238961938ea5df78.tar.xz | |
X86: Flesh out register indexing constants.
--HG--
extra : convert_revision : 56eedc076bbb7962c3976599a15ed93c7cb154c0
Diffstat (limited to 'src/arch/x86/isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 098a75370..3a557169f 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -107,6 +107,6 @@ def operands {{ 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 11), 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 12), 'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20), - 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE_BASE + segment', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 50), + 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 50), 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) }}; |