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authorGabe Black <gblack@eecs.umich.edu>2009-02-01 00:18:13 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-02-01 00:18:13 -0800
commitd432bd13b2f4796a4a9a97831c521ab66aadc414 (patch)
tree35c19f85cf7a6533db5bed75656a910cc1798935 /src/arch/x86/isa
parentf3b8371dfcad39c609e4bf5ecf50c17e57fca805 (diff)
downloadgem5-d432bd13b2f4796a4a9a97831c521ab66aadc414.tar.xz
X86: Fix some incorrect register widths.
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/operands.isa4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index a409d1f0f..d46741f00 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -159,7 +159,7 @@ def operands {{
'CSAttr': ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208),
'MiscRegDest': ('ControlReg', 'uqw', 'dest', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 209),
'MiscRegSrc1': ('ControlReg', 'uqw', 'src1', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 210),
- 'TscOp': ('ControlReg', 'udw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 211),
- 'M5Reg': ('ControlReg', 'udw', 'MISCREG_M5_REG', (None, None, None), 212),
+ 'TscOp': ('ControlReg', 'uqw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 211),
+ 'M5Reg': ('ControlReg', 'uqw', 'MISCREG_M5_REG', (None, None, None), 212),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300)
}};