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| author | Bjoern A. Zeeb <baz21@cam.ac.uk> | 2017-09-26 16:36:05 +0000 |
|---|---|---|
| committer | B.A. Zeeb <baz21@cam.ac.uk> | 2017-09-27 22:13:22 +0000 |
| commit | 0b77e05cb21ad946f12b67cf3336ba92b2a1a522 (patch) | |
| tree | 9c6902ae90ad6a4c8ae0c03168f5709dc4d85180 /src/arch/x86/isa | |
| parent | 9eac6c5ce50930d9c92bdf7f9a5f875c3cfd16f8 (diff) | |
| download | gem5-0b77e05cb21ad946f12b67cf3336ba92b2a1a522.tar.xz | |
arch-x86: fix CondInst decoding for MOV to Control Registers
MOV Rd,Cd is MR encoded but the control register is operand 2
not operand 1 hence this needs to be MODRM_REG not MODRM_RM.
While MOV Cd,Rd is RM encoded registers are also swapped, so
it also needs to be MODRM_REG as well (as it already correctly is).
This fixes incorrect UD2 reportings leading to invalid traps
reported in O3 on X86 FS introduced with 4e939a7 .
Change-Id: Ib33c8ba87b00e0264d33da44fff64ed9e4d2d9d8
Reviewed-on: https://gem5-review.googlesource.com/4861
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/x86/isa')
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index 8b8756823..f0698ce18 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -361,7 +361,7 @@ // no prefix 0x0: decode OPCODE_OP_BOTTOM3 { 0x0: CondInst::MOV( - {{isValidMiscReg(MISCREG_CR(MODRM_RM))}},Rd,Cd); + {{isValidMiscReg(MISCREG_CR(MODRM_REG))}},Rd,Cd); 0x1: MOV(Rd,Dd); 0x2: CondInst::MOV( {{isValidMiscReg(MISCREG_CR(MODRM_REG))}},Cd,Rd); |