Pull some hard coded base classes out of the isa description.

--HG--
rename : src/arch/x86/isa/base.isa => src/arch/x86/isa/outputblock.isa
extra : convert_revision : 7954e7d5eea3b5966c9e273a08bcd169a39f380c

11 files changed, 117 insertions, 510 deletions

diff --git a/src/arch/x86/isa/base.isa b/src/arch/x86/isa/base.isa
deleted file mode 100644
index eed969b47..000000000
--- a/src/arch/x86/isa/base.isa
+++ /dev/null
@@ -1,303 +0,0 @@
-// Copyright (c) 2007 The Hewlett-Packard Development Company
-// All rights reserved.
-//
-// Redistribution and use of this software in source and binary forms,
-// with or without modification, are permitted provided that the
-// following conditions are met:
-//
-// The software must be used only for Non-Commercial Use which means any
-// use which is NOT directed to receiving any direct monetary
-// compensation for, or commercial advantage from such use.  Illustrative
-// examples of non-commercial use are academic research, personal study,
-// teaching, education and corporate research & development.
-// Illustrative examples of commercial use are distributing products for
-// commercial advantage and providing services using the software for
-// commercial advantage.
-//
-// If you wish to use this software or functionality therein that may be
-// covered by patents for commercial use, please contact:
-//     Director of Intellectual Property Licensing
-//     Office of Strategy and Technology
-//     Hewlett-Packard Company
-//     1501 Page Mill Road
-//     Palo Alto, California  94304
-//
-// Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.  Redistributions
-// in binary form must reproduce the above copyright notice, this list of
-// conditions and the following disclaimer in the documentation and/or
-// other materials provided with the distribution.  Neither the name of
-// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.  No right of
-// sublicense is granted herewith.  Derivatives of the software and
-// output created using the software may be prepared, but only for
-// Non-Commercial Uses.  Derivatives of the software may be shared with
-// others provided: (i) the others agree to abide by the list of
-// conditions herein which includes the Non-Commercial Use restrictions;
-// and (ii) such Derivatives of the software include the above copyright
-// notice to acknowledge the contribution from this software where
-// applicable, this list of conditions and the disclaimer below.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Gabe Black
-
-////////////////////////////////////////////////////////////////////
-//
-// Base class for sparc instructions, and some support functions
-//
-
-let {{
-    # This class will help make dealing with output a little less verbose
-    class OutputBlocks(object):
-        def __init__(self, header_output="",
-                           decoder_output="",
-                           decode_block="",
-                           exec_output=""):
-            self.header_output = header_output
-            self.decoder_output = decoder_output
-            self.decode_block = decode_block
-            self.exec_output = exec_output
-
-        def append(self, blocks):
-            if isinstance(blocks, list) or isinstance(blocks, tuple):
-                assert(len(blocks) == 4)
-                self.header_output += blocks[0]
-                self.decoder_output += blocks[1]
-                self.decode_block += blocks[2]
-                self.exec_output += blocks[3]
-            else:
-                self.header_output += blocks.header_output
-                self.decoder_output += blocks.decoder_output
-                self.decode_block += blocks.decode_block
-                self.exec_output += blocks.exec_output
-
-        def makeList(self):
-            return (self.header_output,
-                    self.decoder_output,
-                    self.decode_block,
-                    self.exec_output)
-}};
-
-output header {{
-
-        /**
-         * Base class for all X86 static instructions.
-         */
-        BitUnion64(X86IntReg)
-            Bitfield<63,0> R;
-            Bitfield<31,0> E;
-            Bitfield<15,0> X;
-            Bitfield<15,8> H;
-            Bitfield<7, 0> L;
-        EndBitUnion(X86IntReg)
-
-        class X86StaticInst : public StaticInst
-        {
-          protected:
-            // Constructor.
-            X86StaticInst(const char *mnem,
-                 ExtMachInst _machInst, OpClass __opClass)
-                    : StaticInst(mnem, _machInst, __opClass)
-                {
-                }
-
-            std::string generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const;
-
-            void printReg(std::ostream &os, int reg) const;
-            void printSrcReg(std::ostream &os, int reg) const;
-            void printDestReg(std::ostream &os, int reg) const;
-
-            inline uint64_t merge(uint64_t into, uint64_t val, int size) const
-            {
-                X86IntReg reg;
-                reg = into;
-                //FIXME This needs to be handle high bytes as well
-                switch(size)
-                {
-                  case 1:
-                    reg.L = val;
-                    break;
-                  case 2:
-                    reg.X = val;
-                    break;
-                  case 4:
-                    //XXX Check if this should be zeroed or sign extended
-                    reg = 0;
-                    reg.E = val;
-                    break;
-                  case 8:
-                    reg.R = val;
-                    break;
-                  default:
-                    panic("Tried to merge with unrecognized size %d.\n", size);
-                }
-                return val;
-            }
-
-            inline uint64_t pick(uint64_t from, int size)
-            {
-                X86IntReg reg;
-                reg = from;
-                switch(size)
-                {
-                  case 1:
-                    return reg.L;
-                  case 2:
-                    return reg.E;
-                  case 4:
-                    return reg.X;
-                  case 8:
-                    return reg.R;
-                  default:
-                    panic("Tried to pick with unrecognized size %d.\n", size);
-                }
-            }
-
-        };
-}};
-
-output decoder {{
-
-        inline void printMnemonic(std::ostream &os, const char * mnemonic)
-        {
-            ccprintf(os, "\t%s   ", mnemonic);
-        }
-
-        inline void printMnemonic(std::ostream &os,
-                const char * instMnemonic, const char * mnemonic)
-        {
-            ccprintf(os, "\t%s : %s   ", instMnemonic, mnemonic);
-        }
-
-        void printSegment(std::ostream &os, int segment)
-        {
-            switch (segment)
-            {
-              case 0:
-                ccprintf(os, "ES");
-                break;
-              case 1:
-                ccprintf(os, "CS");
-                break;
-              case 2:
-                ccprintf(os, "SS");
-                break;
-              case 3:
-                ccprintf(os, "DS");
-                break;
-              case 4:
-                ccprintf(os, "FS");
-                break;
-              case 5:
-                ccprintf(os, "GS");
-                break;
-              default:
-                panic("Unrecognized segment %d\n", segment);
-            }
-        }
-
-        void
-        X86StaticInst::printSrcReg(std::ostream &os, int reg) const
-        {
-            if(_numSrcRegs > reg)
-                printReg(os, _srcRegIdx[reg]);
-        }
-
-        void
-        X86StaticInst::printDestReg(std::ostream &os, int reg) const
-        {
-            if(_numDestRegs > reg)
-                printReg(os, _destRegIdx[reg]);
-        }
-
-        void
-        X86StaticInst::printReg(std::ostream &os, int reg) const
-        {
-            if (reg < FP_Base_DepTag) {
-                //FIXME These should print differently depending on the
-                //mode etc, but for now this will get the point across
-                switch (reg) {
-                  case INTREG_RAX:
-                    ccprintf(os, "rax");
-                    break;
-                  case INTREG_RBX:
-                    ccprintf(os, "rbx");
-                    break;
-                  case INTREG_RCX:
-                    ccprintf(os, "rcx");
-                    break;
-                  case INTREG_RDX:
-                    ccprintf(os, "rdx");
-                    break;
-                  case INTREG_RSP:
-                    ccprintf(os, "rsp");
-                    break;
-                  case INTREG_RBP:
-                    ccprintf(os, "rbp");
-                    break;
-                  case INTREG_RSI:
-                    ccprintf(os, "rsi");
-                    break;
-                  case INTREG_RDI:
-                    ccprintf(os, "rdi");
-                    break;
-                  case INTREG_R8W:
-                    ccprintf(os, "r8");
-                    break;
-                  case INTREG_R9W:
-                    ccprintf(os, "r9");
-                    break;
-                  case INTREG_R10W:
-                    ccprintf(os, "r10");
-                    break;
-                  case INTREG_R11W:
-                    ccprintf(os, "r11");
-                    break;
-                  case INTREG_R12W:
-                    ccprintf(os, "r12");
-                    break;
-                  case INTREG_R13W:
-                    ccprintf(os, "r13");
-                    break;
-                  case INTREG_R14W:
-                    ccprintf(os, "r14");
-                    break;
-                  case INTREG_R15W:
-                    ccprintf(os, "r15");
-                    break;
-                  default:
-                    ccprintf(os, "t%d", reg - NUM_INTREGS);
-                }
-            } else if (reg < Ctrl_Base_DepTag) {
-                ccprintf(os, "%%f%d", reg - FP_Base_DepTag);
-            } else {
-                switch (reg - Ctrl_Base_DepTag) {
-                  default:
-                    ccprintf(os, "%%ctrl%d", reg - Ctrl_Base_DepTag);
-                }
-            }
-        }
-
-        std::string X86StaticInst::generateDisassembly(Addr pc,
-            const SymbolTable *symtab) const
-        {
-            std::stringstream ss;
-
-            printMnemonic(ss, mnemonic);
-
-            return ss.str();
-        }
-}};
diff --git a/src/arch/x86/isa/formats/unimp.isa b/src/arch/x86/isa/formats/unimp.isa
index 12fa8387b..183beb3b8 100644
--- a/src/arch/x86/isa/formats/unimp.isa
+++ b/src/arch/x86/isa/formats/unimp.isa
@@ -68,12 +68,12 @@ output header {{
      * 'Unknown' class is used for unrecognized/illegal instructions.
      * This is a leaf class.
      */
-    class FailUnimplemented : public X86StaticInst
+    class FailUnimplemented : public X86ISA::X86StaticInst
     {
       public:
         /// Constructor
         FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
-            : X86StaticInst(_mnemonic, _machInst, No_OpClass)
+            : X86ISA::X86StaticInst(_mnemonic, _machInst, No_OpClass)
         {
             // don't call execute() (which panics) if we're on a
             // speculative path
@@ -95,7 +95,7 @@ output header {{
      * probably make the 'warned' flag a static member of the derived
      * class.
      */
-    class WarnUnimplemented : public X86StaticInst
+    class WarnUnimplemented : public X86ISA::X86StaticInst
     {
       private:
         /// Have we warned on this instruction yet?
@@ -104,7 +104,7 @@ output header {{
       public:
         /// Constructor
         WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
-            : X86StaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
+            : X86ISA::X86StaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
         {
             // don't call execute() (which panics) if we're on a
             // speculative path
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 4f27c72f5..d1c76c252 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -97,6 +97,9 @@ output header {{
 #include <iostream>
 
 #include "arch/x86/emulenv.hh"
+#include "arch/x86/insts/microldstop.hh"
+#include "arch/x86/insts/microregop.hh"
+#include "arch/x86/insts/static_inst.hh"
 #include "arch/x86/isa_traits.hh"
 #include "arch/x86/regfile.hh"
 #include "arch/x86/types.hh"
diff --git a/src/arch/x86/isa/main.isa b/src/arch/x86/isa/main.isa
index fed8903c0..73cebc12b 100644
--- a/src/arch/x86/isa/main.isa
+++ b/src/arch/x86/isa/main.isa
@@ -79,8 +79,8 @@ namespace X86ISA;
 //Include the bitfield definitions
 ##include "bitfields.isa"
 
-//Include the base class for x86 instructions, and some support code.
-##include "base.isa"
+//Include the OutputBlocks class which is used to bundle output.
+##include "outputblock.isa"
 
 //Include the definitions for the instruction formats
 ##include "formats/formats.isa"
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index ee2b92f53..afe8ae64c 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -56,9 +56,9 @@
 // Authors: Gabe Black
 
 //Include the definitions of the micro ops.
-//These are StaticInst classes which stand on their own and make up an
-//internal instruction set, and also python representations which are passed
-//into the microcode assembler.
+//These are python representations of static insts which stand on their own
+//and make up an internal instruction set. They are used by the micro
+//assembler.
 ##include "microops/microops.isa"
 
 //Include code to build macroops in both C++ and python.
diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa
index 79ac4493a..71fc3b3a5 100644
--- a/src/arch/x86/isa/microops/base.isa
+++ b/src/arch/x86/isa/microops/base.isa
@@ -61,42 +61,6 @@ let {{
     microopClasses = {}
 }};
 
-//A class which is the base of all x86 micro ops. It provides a function to
-//set necessary flags appropriately.
-output header {{
-    class X86MicroopBase : public X86StaticInst
-    {
-      protected:
-        const char * instMnem;
-        uint8_t opSize;
-        uint8_t addrSize;
-
-        X86MicroopBase(ExtMachInst _machInst,
-                const char *mnem, const char *_instMnem,
-                bool isMicro, bool isDelayed,
-                bool isFirst, bool isLast,
-                OpClass __opClass) :
-            X86StaticInst(mnem, _machInst, __opClass),
-            instMnem(_instMnem)
-        {
-            flags[IsMicroop] = isMicro;
-            flags[IsDelayedCommit] = isDelayed;
-            flags[IsFirstMicroop] = isFirst;
-            flags[IsLastMicroop] = isLast;
-        }
-
-        std::string generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-            std::stringstream ss;
-
-            ccprintf(ss, "\t%s.%s", instMnem, mnemonic);
-
-            return ss.str();
-        }
-    };
-}};
-
 //////////////////////////////////////////////////////////////////////////
 //
 // Base class for the python representation of x86 microops
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index fbff899a0..2e98a42bf 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -59,63 +59,6 @@
 //
 //////////////////////////////////////////////////////////////////////////
 
-output header {{
-    /**
-     * Base class for load and store ops
-     */
-    class LdStOp : public X86MicroopBase
-    {
-      protected:
-        const uint8_t scale;
-        const RegIndex index;
-        const RegIndex base;
-        const uint64_t disp;
-        const uint8_t segment;
-        const RegIndex data;
-        const uint8_t dataSize;
-        const uint8_t addressSize;
-
-        //Constructor
-        LdStOp(ExtMachInst _machInst,
-                const char * mnem, const char * _instMnem,
-                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
-                uint8_t _scale, RegIndex _index, RegIndex _base,
-                uint64_t _disp, uint8_t _segment,
-                RegIndex _data,
-                uint8_t _dataSize, uint8_t _addressSize,
-                OpClass __opClass) :
-        X86MicroopBase(machInst, mnem, _instMnem,
-                isMicro, isDelayed, isFirst, isLast, __opClass),
-                scale(_scale), index(_index), base(_base),
-                disp(_disp), segment(_segment),
-                data(_data),
-                dataSize(_dataSize), addressSize(_addressSize)
-        {}
-
-        std::string generateDisassembly(Addr pc,
-            const SymbolTable *symtab) const;
-    };
-}};
-
-output decoder {{
-    std::string LdStOp::generateDisassembly(Addr pc,
-            const SymbolTable *symtab) const
-    {
-        std::stringstream response;
-
-        printMnemonic(response, instMnem, mnemonic);
-        printReg(response, data);
-        response << ", ";
-        printSegment(response, segment);
-        ccprintf(response, ":[%d*", scale);
-        printReg(response, index);
-        response << " + ";
-        printReg(response, base);
-        ccprintf(response, " + %#x]", disp);
-        return response.str();
-    }
-}};
-
 // LEA template
 
 def template MicroLeaExecute {{
@@ -424,7 +367,7 @@ let {{
         name = mnemonic.lower()
 
         # Build up the all register version of this micro op
-        iop = InstObjParams(name, Name, 'LdStOp',
+        iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
                 {"code": code, "ea_code": calculateEA})
         header_output += MicroLdStOpDeclare.subst(iop)
         decoder_output += MicroLdStOpConstructor.subst(iop)
@@ -451,7 +394,7 @@ let {{
         name = mnemonic.lower()
 
         # Build up the all register version of this micro op
-        iop = InstObjParams(name, Name, 'LdStOp',
+        iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
                 {"code": code, "ea_code": calculateEA})
         header_output += MicroLdStOpDeclare.subst(iop)
         decoder_output += MicroLdStOpConstructor.subst(iop)
@@ -469,7 +412,7 @@ let {{
 
     defineMicroLoadOp('St', 'Mem = Data;')
 
-    iop = InstObjParams("lea", "Lea", 'LdStOp',
+    iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
             {"code": "Data = merge(Data, EA, dataSize);", "ea_code": calculateEA})
     header_output += MicroLeaDeclare.subst(iop)
     decoder_output += MicroLdStOpConstructor.subst(iop)
diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa
index 141d7523f..177a914ae 100644
--- a/src/arch/x86/isa/microops/limmop.isa
+++ b/src/arch/x86/isa/microops/limmop.isa
@@ -72,7 +72,7 @@ def template MicroLimmOpExecute {{
 }};
 
 def template MicroLimmOpDeclare {{
-    class %(class_name)s : public X86MicroopBase
+    class %(class_name)s : public X86ISA::X86MicroopBase
     {
       protected:
         const RegIndex dest;
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 65b75fab8..542b517fb 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -59,100 +59,6 @@
 //
 //////////////////////////////////////////////////////////////////////////
 
-output header {{
-    /**
-     * Base classes for RegOps which provides a generateDisassembly method.
-     */
-    class RegOp : public X86MicroopBase
-    {
-      protected:
-        const RegIndex src1;
-        const RegIndex src2;
-        const RegIndex dest;
-        const bool setStatus;
-        const uint8_t dataSize;
-        const uint8_t ext;
-
-        // Constructor
-        RegOp(ExtMachInst _machInst,
-                const char *mnem, const char *_instMnem,
-                bool isMicro, bool isDelayed,
-                bool isFirst, bool isLast,
-                RegIndex _src1, RegIndex _src2, RegIndex _dest,
-                bool _setStatus, uint8_t _dataSize, uint8_t _ext,
-                OpClass __opClass) :
-            X86MicroopBase(_machInst, mnem, _instMnem,
-                    isMicro, isDelayed, isFirst, isLast,
-                    __opClass),
-            src1(_src1), src2(_src2), dest(_dest),
-            setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
-        {
-        }
-
-        std::string generateDisassembly(Addr pc,
-            const SymbolTable *symtab) const;
-    };
-
-    class RegOpImm : public X86MicroopBase
-    {
-      protected:
-        const RegIndex src1;
-        const uint8_t imm8;
-        const RegIndex dest;
-        const bool setStatus;
-        const uint8_t dataSize;
-        const uint8_t ext;
-
-        // Constructor
-        RegOpImm(ExtMachInst _machInst,
-                const char * mnem, const char *_instMnem,
-                bool isMicro, bool isDelayed,
-                bool isFirst, bool isLast,
-                RegIndex _src1, uint8_t _imm8, RegIndex _dest,
-                bool _setStatus, uint8_t _dataSize, uint8_t _ext,
-                OpClass __opClass) :
-            X86MicroopBase(_machInst, mnem, _instMnem,
-                    isMicro, isDelayed, isFirst, isLast,
-                    __opClass),
-            src1(_src1), imm8(_imm8), dest(_dest),
-            setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
-        {
-        }
-
-        std::string generateDisassembly(Addr pc,
-            const SymbolTable *symtab) const;
-    };
-}};
-
-output decoder {{
-    std::string RegOp::generateDisassembly(Addr pc,
-            const SymbolTable *symtab) const
-    {
-        std::stringstream response;
-
-        printMnemonic(response, instMnem, mnemonic);
-        printReg(response, dest);
-        response << ", ";
-        printReg(response, src1);
-        response << ", ";
-        printReg(response, src2);
-        return response.str();
-    }
-
-    std::string RegOpImm::generateDisassembly(Addr pc,
-            const SymbolTable *symtab) const
-    {
-        std::stringstream response;
-
-        printMnemonic(response, instMnem, mnemonic);
-        printReg(response, dest);
-        response << ", ";
-        printReg(response, src1);
-        ccprintf(response, ", %#x", imm8);
-        return response.str();
-    }
-}};
-
 def template MicroRegOpExecute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                 Trace::InstRecord *traceData) const
@@ -391,7 +297,8 @@ let {{
                 self.className = Name
                 self.mnemonic = name
 
-        setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, flagCode);
+        setUpMicroRegOp(name, Name, "X86ISA::RegOp", \
+                regCode, RegOpChild, flagCode);
 
         # Build the immediate version of this micro op
         class RegOpChildImm(RegOpImm):
@@ -400,7 +307,8 @@ let {{
                 self.className = Name + "Imm"
                 self.mnemonic = name + "i"
 
-        setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, flagCode);
+        setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
+                immCode, RegOpChildImm, flagCode);
 
     defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF
     defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "")
@@ -431,7 +339,7 @@ let {{
                 self.className = Name
                 self.mnemonic = name
 
-        setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, "");
+        setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, RegOpChild, "");
 
         # Build the immediate version of this micro op
         class RegOpChildImm(RegOpImm):
@@ -440,7 +348,8 @@ let {{
                 self.className = Name + "Imm"
                 self.mnemonic = name + "i"
 
-        setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, "");
+        setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
+                immCode, RegOpChildImm, "");
 
     defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2')
 
@@ -455,7 +364,7 @@ let {{
                 self.className = Name
                 self.mnemonic = name
 
-        setUpMicroRegOp(name, Name, "RegOp", code, RegOpChild, "");
+        setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, RegOpChild, "");
 
     defineMicroRegOpRd('Rdip', 'DestReg = RIP')
 
@@ -469,7 +378,7 @@ let {{
                 self.className = Name
                 self.mnemonic = name
 
-        setUpMicroRegOp(name, Name, "RegOpImm", code, RegOpChild, "");
+        setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, RegOpChild, "");
 
     defineMicroRegOpImm('Sext', '''
             IntReg val = SrcReg1;
diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa
index b56223390..4d9957587 100644
--- a/src/arch/x86/isa/microops/specop.isa
+++ b/src/arch/x86/isa/microops/specop.isa
@@ -60,7 +60,7 @@
 //////////////////////////////////////////////////////////////////////////
 
 output header {{
-    class MicroFault : public X86MicroopBase
+    class MicroFault : public X86ISA::X86MicroopBase
     {
       protected:
         Fault fault;
diff --git a/src/arch/x86/isa/outputblock.isa b/src/arch/x86/isa/outputblock.isa
new file mode 100644
index 000000000..342d6ac4b
--- /dev/null
+++ b/src/arch/x86/isa/outputblock.isa
@@ -0,0 +1,91 @@
+// Copyright (c) 2007 The Hewlett-Packard Development Company
+// All rights reserved.
+//
+// Redistribution and use of this software in source and binary forms,
+// with or without modification, are permitted provided that the
+// following conditions are met:
+//
+// The software must be used only for Non-Commercial Use which means any
+// use which is NOT directed to receiving any direct monetary
+// compensation for, or commercial advantage from such use.  Illustrative
+// examples of non-commercial use are academic research, personal study,
+// teaching, education and corporate research & development.
+// Illustrative examples of commercial use are distributing products for
+// commercial advantage and providing services using the software for
+// commercial advantage.
+//
+// If you wish to use this software or functionality therein that may be
+// covered by patents for commercial use, please contact:
+//     Director of Intellectual Property Licensing
+//     Office of Strategy and Technology
+//     Hewlett-Packard Company
+//     1501 Page Mill Road
+//     Palo Alto, California  94304
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.  Redistributions
+// in binary form must reproduce the above copyright notice, this list of
+// conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution.  Neither the name of
+// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.  No right of
+// sublicense is granted herewith.  Derivatives of the software and
+// output created using the software may be prepared, but only for
+// Non-Commercial Uses.  Derivatives of the software may be shared with
+// others provided: (i) the others agree to abide by the list of
+// conditions herein which includes the Non-Commercial Use restrictions;
+// and (ii) such Derivatives of the software include the above copyright
+// notice to acknowledge the contribution from this software where
+// applicable, this list of conditions and the disclaimer below.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+////////////////////////////////////////////////////////////////////
+//
+// Output blocks which group together code generated by the parser.
+//
+
+let {{
+    # This class will help make dealing with output a little less verbose
+    class OutputBlocks(object):
+        def __init__(self, header_output="",
+                           decoder_output="",
+                           decode_block="",
+                           exec_output=""):
+            self.header_output = header_output
+            self.decoder_output = decoder_output
+            self.decode_block = decode_block
+            self.exec_output = exec_output
+
+        def append(self, blocks):
+            if isinstance(blocks, list) or isinstance(blocks, tuple):
+                assert(len(blocks) == 4)
+                self.header_output += blocks[0]
+                self.decoder_output += blocks[1]
+                self.decode_block += blocks[2]
+                self.exec_output += blocks[3]
+            else:
+                self.header_output += blocks.header_output
+                self.decoder_output += blocks.decoder_output
+                self.decode_block += blocks.decode_block
+                self.exec_output += blocks.exec_output
+
+        def makeList(self):
+            return (self.header_output,
+                    self.decoder_output,
+                    self.decode_block,
+                    self.exec_output)
+}};