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authorSwapnil Haria <swapnilster@gmail.com>2018-01-15 21:49:17 -0600
committerJason Lowe-Power <jason@lowepower.com>2018-01-23 22:17:46 +0000
commit83f2b253989fd6dfc8f48d5368ae351ade91cfc6 (patch)
treec11f04427040c2efedb3cbfea8227293861ba8ff /src/arch/x86/isa
parentb074a15ec16b595cbe00cb63e2feff40059b60fb (diff)
downloadgem5-83f2b253989fd6dfc8f48d5368ae351ade91cfc6.tar.xz
arch-x86: Adding clflush, clflushopt, clwb instructions
This patch adds support for cache flushing instructions in x86. It piggybacks on support for similar instructions in arm ISA added by Nikos Nikoleris. I have tested each instruction using microbenchmarks. Change-Id: I72b6b8dc30c236a21eff7958fa231f0663532d7d Reviewed-on: https://gem5-review.googlesource.com/7401 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa12
-rw-r--r--src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py37
-rw-r--r--src/arch/x86/isa/microops/ldstop.isa5
3 files changed, 50 insertions, 4 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index f0698ce18..aa60e4c48 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -800,8 +800,16 @@
0x3: Inst::STMXCSR(Md);
0x4: xsave();
0x5: xrstor();
- 0x6: Inst::UD2();
- 0x7: clflush();
+ 0x6: decode LEGACY_DECODEVAL {
+ 0x0: Inst::UD2();
+ 0x1: Inst::CLWB(Mb);
+ default: Inst::UD2();
+ }
+ 0x7: decode LEGACY_DECODEVAL {
+ 0x0: Inst::CLFLUSH(Mb);
+ 0x1: Inst::CLFLUSHOPT(Mb);
+ default: Inst::CLFLUSH(Mb);
+ }
}
}
0x7: Inst::IMUL(Gv,Ev);
diff --git a/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py b/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
index d42c68795..4dc0b308e 100644
--- a/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
+++ b/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
@@ -58,6 +58,41 @@ def macroop PREFETCH_T0_P
ld t0, seg, riprel, disp, dataSize=1, prefetch=True
};
+def macroop CLFLUSH_M
+{
+ clflushopt t0, seg, sib, disp, dataSize=1
+ mfence
+};
+
+def macroop CLFLUSH_P
+{
+ rdip t7
+ clflushopt t0, seg, riprel, disp, dataSize=1
+ mfence
+};
+
+def macroop CLFLUSHOPT_M
+{
+ clflushopt t0, seg, sib, disp, dataSize=1
+};
+
+def macroop CLFLUSHOPT_P
+{
+ rdip t7
+ clflushopt t0, seg, riprel, disp, dataSize=1
+};
+
+def macroop CLWB_M
+{
+ clwb t1, seg, sib, disp, dataSize=1
+};
+
+def macroop CLWB_P
+{
+ rdip t7
+ clwb t1, seg, riprel, disp, dataSize=1
+};
+
'''
#let {{
@@ -71,6 +106,4 @@ def macroop PREFETCH_T0_P
# "GenFault ${new UnimpInstFault}"
# class PREFETCHW(Inst):
# "GenFault ${new UnimpInstFault}"
-# class CLFLUSH(Inst):
-# "GenFault ${new UnimpInstFault}"
#}};
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index a3d9c5a70..83e24e154 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -634,6 +634,11 @@ let {{
''')
defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS")
+ defineMicroStoreOp('Clflushopt', 'Mem = 0;',
+ mem_flags="Request::CLEAN | Request::INVALIDATE" +
+ " | Request::DST_POC")
+ defineMicroStoreOp('Clwb', 'Mem = 0;',
+ mem_flags="Request::CLEAN | Request::DST_POC")
def defineMicroStoreSplitOp(mnemonic, code,
completeCode="", mem_flags="0"):