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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 02:53:00 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 02:53:00 -0700 |
| commit | d277feb925bae400fb264656c4b851f1f2db7707 (patch) | |
| tree | bc86f4b8cb52888958aca1ffbf7f5193d5eda3a0 /src/arch/x86/isa | |
| parent | a340b214cfe60dd6272b0f74a3a2a2807b850a6a (diff) | |
| download | gem5-d277feb925bae400fb264656c4b851f1f2db7707.tar.xz | |
X86: Implement the INIT IPI.
Diffstat (limited to 'src/arch/x86/isa')
| -rw-r--r-- | src/arch/x86/isa/insts/romutil.py | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/arch/x86/isa/insts/romutil.py b/src/arch/x86/isa/insts/romutil.py index e47259eb3..17034fd49 100644 --- a/src/arch/x86/isa/insts/romutil.py +++ b/src/arch/x86/isa/insts/romutil.py @@ -209,4 +209,15 @@ def rom panic "Legacy mode interrupts not implemented (in microcode)" eret }; + +def rom +{ + extern initIntHalt: + rflags t1 + limm t2, "~IFBit" + and t1, t1, t2 + wrflags t1, t0 + halt + eret +}; ''' |