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authorGabe Black <gblack@eecs.umich.edu>2007-06-19 14:18:25 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-06-19 14:18:25 +0000
commit6e286cddfaf6286f96e06c26266070f6fbbd7749 (patch)
treef318b62e376304d0b7f353a68794e4da160f5c8e /src/arch/x86/isa_traits.hh
parent8caef7d25a6a150fa6369234bbdc8c14ef637df8 (diff)
downloadgem5-6e286cddfaf6286f96e06c26266070f6fbbd7749.tar.xz
Get rid of the immediate and displacement components of the EmulEnv struct and use them directly out of the instruction. The extra copies are conceptually realistic but are just innefficient as implemented. Also don't use the zeroeth microcode register for general storage since it's now the zero register, and implement a load and a store microops.
--HG-- extra : convert_revision : 0686296ca8b72940d961ecc6051063bfda1e932d
Diffstat (limited to 'src/arch/x86/isa_traits.hh')
-rw-r--r--src/arch/x86/isa_traits.hh2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 7aba6248a..4c02ee35e 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -93,7 +93,7 @@ namespace X86ISA
// semantically meaningful register indices
//There is no such register in X86
- const int ZeroReg = 0;
+ const int ZeroReg = NUM_INTREGS;
const int StackPointerReg = INTREG_RSP;
//X86 doesn't seem to have a link register
const int ReturnAddressReg = 0;