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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-17 11:31:22 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-17 11:31:22 -0500 |
| commit | 0ef3dcc27b0fd03df0aa38a4af05bf536be29c49 (patch) | |
| tree | 9a3494b6304b6139524340c2ce6e9d5e869a7028 /src/arch/x86/isa_traits.hh | |
| parent | fc5bf6713f191047e07f33a788d099b2bbd9faf4 (diff) | |
| download | gem5-0ef3dcc27b0fd03df0aa38a4af05bf536be29c49.tar.xz | |
x86: decode instructions with vex prefix
This patch updates the x86 decoder so that it can decode instructions with vex
prefix. It also updates the isa with opcodes from vex opcode maps 1, 2 and 3.
Note that none of the instructions have been implemented yet. The
implementations would be provided in due course of time.
Diffstat (limited to 'src/arch/x86/isa_traits.hh')
| -rw-r--r-- | src/arch/x86/isa_traits.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh index 6e5373ca1..fcdffec1c 100644 --- a/src/arch/x86/isa_traits.hh +++ b/src/arch/x86/isa_traits.hh @@ -71,7 +71,8 @@ namespace X86ISA const ExtMachInst NoopMachInst M5_VAR_USED = { 0x0, // No legacy prefixes. 0x0, // No rex prefix. - { OneByteOpcode, 0x90 }, // One opcode byte, 0x90. + 0x0, // No two / three byte escape sequence + { OneByteOpcode, 0x90 }, // One opcode byte, 0x90. 0x0, 0x0, // No modrm or sib. 0, 0, // No immediate or displacement. 8, 8, 8, // All sizes are 8. |