summaryrefslogtreecommitdiff
path: root/src/arch/x86/isa_traits.hh
diff options
context:
space:
mode:
authorGabe Black <gabeblack@google.com>2017-12-20 00:06:07 -0800
committerGabe Black <gabeblack@google.com>2017-12-23 03:40:20 +0000
commitda79d6c6cde0fbe5473ce868c9be4771160a003b (patch)
tree77c5a39da84ccca689ffaad123bd84002e13eda5 /src/arch/x86/isa_traits.hh
parent87eb9a3a640875d176bec9dfb130450d23d8e8b8 (diff)
downloadgem5-da79d6c6cde0fbe5473ce868c9be4771160a003b.tar.xz
alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst.
It's no longer used. Change-Id: I4a71bcb214f1bb186b92ef50841eca635e6701c5 Reviewed-on: https://gem5-review.googlesource.com/6826 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/x86/isa_traits.hh')
-rw-r--r--src/arch/x86/isa_traits.hh17
1 files changed, 0 insertions, 17 deletions
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 88cd16eff..2b19b1ba7 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -56,10 +56,6 @@ namespace X86ISA
// X86 does not have a delay slot
#define ISA_HAS_DELAY_SLOT 0
- // X86 NOP (XCHG rAX, rAX)
- //XXX This needs to be set to an intermediate instruction struct
- //which encodes this instruction
-
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
@@ -68,19 +64,6 @@ namespace X86ISA
const bool CurThreadInfoImplemented = false;
const int CurThreadInfoReg = -1;
-
- const ExtMachInst NoopMachInst M5_VAR_USED = {
- 0x0, // No legacy prefixes.
- 0x0, // No rex prefix.
- 0x0, // No two / three byte escape sequence
- { OneByteOpcode, 0x90 }, // One opcode byte, 0x90.
- 0x0, 0x0, // No modrm or sib.
- 0, 0, // No immediate or displacement.
- 8, 8, 8, // All sizes are 8.
- 0, // Displacement size is 0.
- SixtyFourBitMode // Behave as if we're in 64 bit
- // mode (this doesn't actually matter).
- };
}
#endif // __ARCH_X86_ISATRAITS_HH__