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author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-07-22 08:10:59 -0700 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-07-22 08:10:59 -0700 |
commit | d5c74657c986a1c6730393d76da6d8859ae7fca4 (patch) | |
tree | 9de36c35735432220f010b98a25b0f380d13ef6a /src/arch/x86/miscregfile.cc | |
parent | 1c2d5f5e64387527efe495a59f6946e7b539a543 (diff) | |
parent | 03730edc45e2e00bdec58dabc84e94c632634a1a (diff) | |
download | gem5-d5c74657c986a1c6730393d76da6d8859ae7fca4.tar.xz |
Merge more changes in from head.
--HG--
extra : convert_revision : 8f170f2754eccdb424a35b5b077225abcf6eee72
Diffstat (limited to 'src/arch/x86/miscregfile.cc')
-rw-r--r-- | src/arch/x86/miscregfile.cc | 47 |
1 files changed, 41 insertions, 6 deletions
diff --git a/src/arch/x86/miscregfile.cc b/src/arch/x86/miscregfile.cc index 14ba3c7cc..9d8e94061 100644 --- a/src/arch/x86/miscregfile.cc +++ b/src/arch/x86/miscregfile.cc @@ -86,6 +86,7 @@ */ #include "arch/x86/miscregfile.hh" +#include "sim/serialize.hh" using namespace X86ISA; using namespace std; @@ -105,31 +106,65 @@ void MiscRegFile::clear() MiscReg MiscRegFile::readRegNoEffect(int miscReg) { - panic("No misc registers in x86 yet!\n"); + switch(miscReg) + { + case MISCREG_CR1: + case MISCREG_CR5: + case MISCREG_CR6: + case MISCREG_CR7: + case MISCREG_CR9: + case MISCREG_CR10: + case MISCREG_CR11: + case MISCREG_CR12: + case MISCREG_CR13: + case MISCREG_CR14: + case MISCREG_CR15: + panic("Tried to read invalid control register %d\n", miscReg); + break; + } + return regVal[miscReg]; } MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc) { - panic("No misc registers in x86 yet!\n"); + warn("No miscreg effects implemented yet!\n"); + return readRegNoEffect(miscReg); } void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val) { - panic("No misc registers in x86 yet!\n"); + switch(miscReg) + { + case MISCREG_CR1: + case MISCREG_CR5: + case MISCREG_CR6: + case MISCREG_CR7: + case MISCREG_CR9: + case MISCREG_CR10: + case MISCREG_CR11: + case MISCREG_CR12: + case MISCREG_CR13: + case MISCREG_CR14: + case MISCREG_CR15: + panic("Tried to write invalid control register %d\n", miscReg); + break; + } + regVal[miscReg] = val; } void MiscRegFile::setReg(int miscReg, const MiscReg &val, ThreadContext * tc) { - panic("No misc registers in x86 yet!\n"); + warn("No miscreg effects implemented yet!\n"); + setRegNoEffect(miscReg, val); } void MiscRegFile::serialize(std::ostream & os) { - panic("No misc registers in x86 yet!\n"); + SERIALIZE_ARRAY(regVal, NumMiscRegs); } void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section) { - panic("No misc registers in x86 yet!\n"); + UNSERIALIZE_ARRAY(regVal, NumMiscRegs); } |