X86: Reorganize segmentation and implement segment selector movs.

--HG--
extra : convert_revision : 553c3ffeda1f5312cf02493f602e7d4ba2fe66e8

1 files changed, 25 insertions, 0 deletions

diff --git a/src/arch/x86/miscregfile.cc b/src/arch/x86/miscregfile.cc
index a01902478..05d64f73f 100644
--- a/src/arch/x86/miscregfile.cc
+++ b/src/arch/x86/miscregfile.cc
@@ -205,6 +205,31 @@ void MiscRegFile::setReg(int miscReg,
                 }
             }
         }
+      // These segments always actually use their bases, or in other words
+      // their effective bases must stay equal to their actual bases.
+      case MISCREG_FS:
+      case MISCREG_GS:
+      case MISCREG_HS:
+      case MISCREG_TSL:
+      case MISCREG_TSG:
+      case MISCREG_TR:
+      case MISCREG_IDTR:
+        regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_SEL_BASE)] = val;
+        break;
+      // These segments ignore their bases in 64 bit mode.
+      // their effective bases must stay equal to their actual bases.
+      case MISCREG_ES:
+      case MISCREG_CS:
+      case MISCREG_SS:
+      case MISCREG_DS:
+        {
+            Efer efer = regVal[MISCREG_EFER];
+            SegAttr csAttr = regVal[MISCREG_CS_ATTR];
+            if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode.
+                regVal[MISCREG_SEG_EFF_BASE(miscReg -
+                        MISCREG_SEG_SEL_BASE)] = val;
+        }
+        break;
     }
     setRegNoEffect(miscReg, newVal);
 }