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authorGabe Black <gblack@eecs.umich.edu>2008-06-12 00:39:10 -0400
committerGabe Black <gblack@eecs.umich.edu>2008-06-12 00:39:10 -0400
commit8501a90f59c73896b4eea6d7ce8f1d1cc8685d53 (patch)
tree6e8be3ff12c7092a551ca0e816f622083de39f8c /src/arch/x86/miscregfile.cc
parentd093fcb07924cc4341b8142c448b905dd94f7125 (diff)
downloadgem5-8501a90f59c73896b4eea6d7ce8f1d1cc8685d53.tar.xz
X86: Add in some support for the tsc register.
Diffstat (limited to 'src/arch/x86/miscregfile.cc')
-rw-r--r--src/arch/x86/miscregfile.cc8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/x86/miscregfile.cc b/src/arch/x86/miscregfile.cc
index 5d75af0cf..930bf53c7 100644
--- a/src/arch/x86/miscregfile.cc
+++ b/src/arch/x86/miscregfile.cc
@@ -87,6 +87,7 @@
#include "arch/x86/miscregfile.hh"
#include "arch/x86/tlb.hh"
+#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "sim/serialize.hh"
@@ -178,6 +179,10 @@ MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
break;
}
}
+ switch (miscReg) {
+ case MISCREG_TSC:
+ return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
+ }
return readRegNoEffect(miscReg);
}
@@ -377,6 +382,9 @@ void MiscRegFile::setReg(int miscReg,
MISCREG_SEG_BASE_BASE)] = val;
}
break;
+ case MISCREG_TSC:
+ regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
+ return;
}
setRegNoEffect(miscReg, newVal);
}