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authorSteve Reinhardt <stever@eecs.umich.edu>2007-07-22 10:40:45 -0400
committerSteve Reinhardt <stever@eecs.umich.edu>2007-07-22 10:40:45 -0400
commit03730edc45e2e00bdec58dabc84e94c632634a1a (patch)
treeaffdbffcb174a9cfc0de933f3c240ae5f2813292 /src/arch/x86/miscregfile.cc
parent658eeee50715d9fd334ae3fd3e0e21b6db6de0c4 (diff)
parent2cd454d102b5da828b0fbf4b66ef1a24875e69f6 (diff)
downloadgem5-03730edc45e2e00bdec58dabc84e94c632634a1a.tar.xz
Merge Gabe's changes with mine.
--HG-- extra : convert_revision : f50ed42e7acb3f11e610fd6976eaa8df0c6ba2ab
Diffstat (limited to 'src/arch/x86/miscregfile.cc')
-rw-r--r--src/arch/x86/miscregfile.cc47
1 files changed, 41 insertions, 6 deletions
diff --git a/src/arch/x86/miscregfile.cc b/src/arch/x86/miscregfile.cc
index 14ba3c7cc..9d8e94061 100644
--- a/src/arch/x86/miscregfile.cc
+++ b/src/arch/x86/miscregfile.cc
@@ -86,6 +86,7 @@
*/
#include "arch/x86/miscregfile.hh"
+#include "sim/serialize.hh"
using namespace X86ISA;
using namespace std;
@@ -105,31 +106,65 @@ void MiscRegFile::clear()
MiscReg MiscRegFile::readRegNoEffect(int miscReg)
{
- panic("No misc registers in x86 yet!\n");
+ switch(miscReg)
+ {
+ case MISCREG_CR1:
+ case MISCREG_CR5:
+ case MISCREG_CR6:
+ case MISCREG_CR7:
+ case MISCREG_CR9:
+ case MISCREG_CR10:
+ case MISCREG_CR11:
+ case MISCREG_CR12:
+ case MISCREG_CR13:
+ case MISCREG_CR14:
+ case MISCREG_CR15:
+ panic("Tried to read invalid control register %d\n", miscReg);
+ break;
+ }
+ return regVal[miscReg];
}
MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
{
- panic("No misc registers in x86 yet!\n");
+ warn("No miscreg effects implemented yet!\n");
+ return readRegNoEffect(miscReg);
}
void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
{
- panic("No misc registers in x86 yet!\n");
+ switch(miscReg)
+ {
+ case MISCREG_CR1:
+ case MISCREG_CR5:
+ case MISCREG_CR6:
+ case MISCREG_CR7:
+ case MISCREG_CR9:
+ case MISCREG_CR10:
+ case MISCREG_CR11:
+ case MISCREG_CR12:
+ case MISCREG_CR13:
+ case MISCREG_CR14:
+ case MISCREG_CR15:
+ panic("Tried to write invalid control register %d\n", miscReg);
+ break;
+ }
+ regVal[miscReg] = val;
}
void MiscRegFile::setReg(int miscReg,
const MiscReg &val, ThreadContext * tc)
{
- panic("No misc registers in x86 yet!\n");
+ warn("No miscreg effects implemented yet!\n");
+ setRegNoEffect(miscReg, val);
}
void MiscRegFile::serialize(std::ostream & os)
{
- panic("No misc registers in x86 yet!\n");
+ SERIALIZE_ARRAY(regVal, NumMiscRegs);
}
void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
{
- panic("No misc registers in x86 yet!\n");
+ UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
}