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authorGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:20 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:20 -0700
commit32daf6fc3fd34af0023ae74c2a1f8dd597f87242 (patch)
tree0868fb00a7546d90971bc18acd4f7b0bbce558c0 /src/arch/x86/miscregfile.hh
parent3e2cad8370d99f45ecf4d922d3ac8213e0d72644 (diff)
downloadgem5-32daf6fc3fd34af0023ae74c2a1f8dd597f87242.tar.xz
Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
Diffstat (limited to 'src/arch/x86/miscregfile.hh')
-rw-r--r--src/arch/x86/miscregfile.hh6
1 files changed, 1 insertions, 5 deletions
diff --git a/src/arch/x86/miscregfile.hh b/src/arch/x86/miscregfile.hh
index 74dcbcbea..f2329b7b4 100644
--- a/src/arch/x86/miscregfile.hh
+++ b/src/arch/x86/miscregfile.hh
@@ -99,14 +99,10 @@ class Checkpoint;
namespace X86ISA
{
- //These will have to be updated in the future.
- const int NumMiscArchRegs = NUM_MISCREGS;
- const int NumMiscRegs = NUM_MISCREGS;
-
class MiscRegFile
{
protected:
- MiscReg regVal[NumMiscRegs];
+ MiscReg regVal[NUM_MISCREGS];
void updateHandyM5Reg(Efer efer, CR0 cr0,
SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);