diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:49:50 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:49:50 -0400 |
| commit | e0c20386ac0f8f54db2e8947793b4c2debabcefc (patch) | |
| tree | f3aad0978e98724d3ab08054a031ea3887f047f6 /src/arch/x86/miscregs.hh | |
| parent | 2bb8933f789d65f47a322e1384eb2e500699bf14 (diff) | |
| download | gem5-e0c20386ac0f8f54db2e8947793b4c2debabcefc.tar.xz | |
X86: Add microops and supporting code to manipulate the whole rflags register.
Diffstat (limited to 'src/arch/x86/miscregs.hh')
| -rw-r--r-- | src/arch/x86/miscregs.hh | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh index 83ba3c0c5..90f1d9fda 100644 --- a/src/arch/x86/miscregs.hh +++ b/src/arch/x86/miscregs.hh @@ -82,6 +82,18 @@ namespace X86ISA OFBit = 1 << 11 }; + enum RFLAGBit { + TFBit = 1 << 8, + IFBit = 1 << 9, + NTBit = 1 << 14, + RFBit = 1 << 16, + VMBit = 1 << 17, + ACBit = 1 << 18, + VIFBit = 1 << 19, + VIPBit = 1 << 20, + IDBit = 1 << 21 + }; + enum MiscRegIndex { // Control registers |