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| author | Alexandru Dutu <alexandru.dutu@amd.com> | 2014-11-23 18:01:09 -0800 |
|---|---|---|
| committer | Alexandru Dutu <alexandru.dutu@amd.com> | 2014-11-23 18:01:09 -0800 |
| commit | 1f539f13c32ad5a9187d56a098d4c857639b0e05 (patch) | |
| tree | 7618c3b946d9c25d9b22018f226eee77b6de4aaf /src/arch/x86/pagetable.cc | |
| parent | c11bcb8119273ef91c40a25b8fd9471a887d0ee5 (diff) | |
| download | gem5-1f539f13c32ad5a9187d56a098d4c857639b0e05.tar.xz | |
mem: Page Table map api modification
This patch adds uncacheable/cacheable and read-only/read-write attributes to
the map method of PageTableBase. It also modifies the constructor of TlbEntry
structs for all architectures to consider the new attributes.
Diffstat (limited to 'src/arch/x86/pagetable.cc')
| -rw-r--r-- | src/arch/x86/pagetable.cc | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/arch/x86/pagetable.cc b/src/arch/x86/pagetable.cc index a9ef18129..cd4df42e7 100644 --- a/src/arch/x86/pagetable.cc +++ b/src/arch/x86/pagetable.cc @@ -45,9 +45,11 @@ namespace X86ISA { -TlbEntry::TlbEntry(Addr asn, Addr _vaddr, Addr _paddr) : - paddr(_paddr), vaddr(_vaddr), logBytes(PageShift), writable(true), - user(true), uncacheable(false), global(false), patBit(0), noExec(false) +TlbEntry::TlbEntry(Addr asn, Addr _vaddr, Addr _paddr, + bool uncacheable, bool read_only) : + paddr(_paddr), vaddr(_vaddr), logBytes(PageShift), writable(!read_only), + user(true), uncacheable(uncacheable), global(false), patBit(0), + noExec(false) {} void |