mem: adding architectural page table support for SE mode

This patch enables the use of page tables that are stored in system memory
and respect x86 specification, in SE mode. It defines an architectural
page table for x86 as a MultiLevelPageTable class and puts a placeholder
class for other ISAs page tables, giving the possibility for future
implementation.

1 files changed, 85 insertions, 0 deletions

diff --git a/src/arch/x86/pagetable.hh b/src/arch/x86/pagetable.hh
index 2a7ade853..86e488bdc 100644
--- a/src/arch/x86/pagetable.hh
+++ b/src/arch/x86/pagetable.hh
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
  * Copyright (c) 2007 The Hewlett-Packard Development Company
  * All rights reserved.
  *
@@ -42,11 +43,15 @@
 
 #include <iostream>
 #include <string>
+#include <vector>
 
 #include "base/bitunion.hh"
 #include "base/misc.hh"
 #include "base/types.hh"
 #include "base/trie.hh"
+#include "cpu/thread_context.hh"
+#include "arch/x86/system.hh"
+#include "debug/MMU.hh"
 
 class Checkpoint;
 
@@ -73,6 +78,25 @@ namespace X86ISA
         Bitfield<31, 22> norml2;
     EndBitUnion(VAddr)
 
+    // Unfortunately, the placement of the base field in a page table entry is
+    // very erratic and would make a mess here. It might be moved here at some
+    // point in the future.
+    BitUnion64(PageTableEntry)
+        Bitfield<63> nx;
+        Bitfield<51, 12> base;
+        Bitfield<11, 9> avl;
+        Bitfield<8> g;
+        Bitfield<7> ps;
+        Bitfield<6> d;
+        Bitfield<5> a;
+        Bitfield<4> pcd;
+        Bitfield<3> pwt;
+        Bitfield<2> u;
+        Bitfield<1> w;
+        Bitfield<0> p;
+    EndBitUnion(PageTableEntry)
+
+
     struct TlbEntry
     {
         // The base of the physical page.
@@ -127,6 +151,67 @@ namespace X86ISA
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
     };
+
+    /** The size of each level of the page table expressed in base 2
+     * logarithmic values
+     */
+    const std::vector<uint8_t> PageTableLayout = {9, 9, 9, 9};
+
+    enum PTEField{
+        PTE_NotPresent = 0,
+        PTE_Present,
+        PTE_ReadOnly = 0,
+        PTE_ReadWrite,
+        PTE_Supervisor = 0,
+        PTE_UserSupervisor,
+    };
+
+    /** Page table operations specific to x86 ISA.
+     * Indended to be used as parameter of MultiLevelPageTable.
+     */
+    class PageTableOps
+    {
+      public:
+        void setPTEFields(PageTableEntry& PTE,
+                          uint64_t present = PTE_Present,
+                          uint64_t read_write = PTE_ReadWrite,
+                          uint64_t user_supervisor = PTE_UserSupervisor)
+        {
+            PTE.p = present;
+            PTE.w = read_write;
+            PTE.u = user_supervisor;// both user and supervisor access allowed
+        }
+
+        /** returns the physical memory address of the page table */
+        Addr getBasePtr(ThreadContext* tc)
+        {
+            CR3 cr3 = pageTablePhysAddr;
+            DPRINTF(MMU, "CR3: %d\n", cr3);
+            return cr3.longPdtb;
+        }
+
+        /** returns the page number out of a page table entry */
+        Addr getPnum(PageTableEntry PTE)
+        {
+            return PTE.base;
+        }
+
+        /** sets the page number in a page table entry */
+        void setPnum(PageTableEntry& PTE, Addr paddr)
+        {
+            PTE.base = paddr;
+        }
+
+        /** returns the offsets to index in every level of a page
+         * table, contained in a virtual address
+         */
+        std::vector<uint64_t> getOffsets(Addr vaddr)
+        {
+            X86ISA::VAddr addr(vaddr);
+            return {addr.longl1, addr.longl2, addr.longl3, addr.longl4};
+        }
+    };
+
 }
 
 #endif