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author | Gabe Black <gblack@eecs.umich.edu> | 2012-04-14 23:24:18 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2012-04-14 23:24:18 -0700 |
commit | aacb676220ac1e6049304bef31a39090487da71e (patch) | |
tree | 3a5b4c951e6be13b59b2a0574e8b31032911acf8 /src/arch/x86/pagetable.hh | |
parent | d6031d72df091a71567a7f43649d62b24c80f496 (diff) | |
download | gem5-aacb676220ac1e6049304bef31a39090487da71e.tar.xz |
X86: Use the AddrTrie class to implement the TLB.
This change also adjusts the TlbEntry class so that it stores the number of
address bits wide a page is rather than its size in bytes. In other words,
instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K,
but it's a little harder going the other way.
Diffstat (limited to 'src/arch/x86/pagetable.hh')
-rw-r--r-- | src/arch/x86/pagetable.hh | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/src/arch/x86/pagetable.hh b/src/arch/x86/pagetable.hh index 768de65bc..8a6e71f3b 100644 --- a/src/arch/x86/pagetable.hh +++ b/src/arch/x86/pagetable.hh @@ -46,11 +46,19 @@ #include "base/bitunion.hh" #include "base/misc.hh" #include "base/types.hh" +#include "base/trie.hh" class Checkpoint; namespace X86ISA { + struct TlbEntry; +} + +typedef Trie<Addr, X86ISA::TlbEntry> TlbEntryTrie; + +namespace X86ISA +{ BitUnion64(VAddr) Bitfield<20, 12> longl1; Bitfield<29, 21> longl2; @@ -72,8 +80,8 @@ namespace X86ISA // The beginning of the virtual page this entry maps. Addr vaddr; - // The size of the page this entry represents. - Addr size; + // The size of the page this represents, in address bits. + unsigned logBytes; // Read permission is always available, assuming it isn't blocked by // other mechanisms. @@ -91,6 +99,10 @@ namespace X86ISA bool patBit; // Whether or not memory on this page can be executed. bool noExec; + // A sequence number to keep track of LRU. + uint64_t lruSeq; + + TlbEntryTrie::Handle trieHandle; TlbEntry(Addr asn, Addr _vaddr, Addr _paddr); TlbEntry() {} |