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| author | Gabe Black <gblack@eecs.umich.edu> | 2012-04-14 23:24:18 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2012-04-14 23:24:18 -0700 |
| commit | aacb676220ac1e6049304bef31a39090487da71e (patch) | |
| tree | 3a5b4c951e6be13b59b2a0574e8b31032911acf8 /src/arch/x86/pagetable_walker.hh | |
| parent | d6031d72df091a71567a7f43649d62b24c80f496 (diff) | |
| download | gem5-aacb676220ac1e6049304bef31a39090487da71e.tar.xz | |
X86: Use the AddrTrie class to implement the TLB.
This change also adjusts the TlbEntry class so that it stores the number of
address bits wide a page is rather than its size in bytes. In other words,
instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K,
but it's a little harder going the other way.
Diffstat (limited to 'src/arch/x86/pagetable_walker.hh')
| -rw-r--r-- | src/arch/x86/pagetable_walker.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh index 3cc20b6cd..c4c770884 100644 --- a/src/arch/x86/pagetable_walker.hh +++ b/src/arch/x86/pagetable_walker.hh @@ -132,7 +132,7 @@ namespace X86ISA void initState(ThreadContext * _tc, BaseTLB::Mode _mode, bool _isTiming = false); Fault startWalk(); - Fault startFunctional(Addr &addr, Addr &pageSize); + Fault startFunctional(Addr &addr, unsigned &logBytes); bool recvPacket(PacketPtr pkt); bool isRetrying(); bool wasStarted(); @@ -169,7 +169,7 @@ namespace X86ISA Fault start(ThreadContext * _tc, BaseTLB::Translation *translation, RequestPtr req, BaseTLB::Mode mode); Fault startFunctional(ThreadContext * _tc, Addr &addr, - Addr &pageSize, BaseTLB::Mode mode); + unsigned &logBytes, BaseTLB::Mode mode); MasterPort &getMasterPort(const std::string &if_name, int idx = -1); protected: |