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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-04 09:40:19 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-11 16:55:30 +0000 |
| commit | f54020eb8155371725ab75b0fc5c419287eca084 (patch) | |
| tree | 65d379f7603e689e083e9a58ff4c2e90abd19fbf /src/arch/x86/pagetable_walker.hh | |
| parent | 2113b21996d086dab32b9fd388efe3df241bfbd2 (diff) | |
| download | gem5-f54020eb8155371725ab75b0fc5c419287eca084.tar.xz | |
misc: Using smart pointers for memory Requests
This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.
Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/arch/x86/pagetable_walker.hh')
| -rw-r--r-- | src/arch/x86/pagetable_walker.hh | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh index d5aa631d2..edca24795 100644 --- a/src/arch/x86/pagetable_walker.hh +++ b/src/arch/x86/pagetable_walker.hh @@ -113,12 +113,12 @@ namespace X86ISA bool started; public: WalkerState(Walker * _walker, BaseTLB::Translation *_translation, - RequestPtr _req, bool _isFunctional = false) : - walker(_walker), req(_req), state(Ready), - nextState(Ready), inflight(0), - translation(_translation), - functional(_isFunctional), timing(false), - retrying(false), started(false) + const RequestPtr &_req, bool _isFunctional = false) : + walker(_walker), req(_req), state(Ready), + nextState(Ready), inflight(0), + translation(_translation), + functional(_isFunctional), timing(false), + retrying(false), started(false) { } void initState(ThreadContext * _tc, BaseTLB::Mode _mode, @@ -157,7 +157,7 @@ namespace X86ISA public: // Kick off the state machine. Fault start(ThreadContext * _tc, BaseTLB::Translation *translation, - RequestPtr req, BaseTLB::Mode mode); + const RequestPtr &req, BaseTLB::Mode mode); Fault startFunctional(ThreadContext * _tc, Addr &addr, unsigned &logBytes, BaseTLB::Mode mode); BaseMasterPort &getMasterPort(const std::string &if_name, |