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author | William Wang <william.wang@arm.com> | 2012-03-30 09:40:11 -0400 |
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committer | William Wang <william.wang@arm.com> | 2012-03-30 09:40:11 -0400 |
commit | f9d403a7b95c50a8b75f8442101eb87ca465f967 (patch) | |
tree | a8302eb02dd5947d53b9437cc19d552145267189 /src/arch/x86/pagetable_walker.hh | |
parent | a14013af3a9e04d68985aea7bcff6c1e70bdbb82 (diff) | |
download | gem5-f9d403a7b95c50a8b75f8442101eb87ca465f967.tar.xz |
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
Diffstat (limited to 'src/arch/x86/pagetable_walker.hh')
-rw-r--r-- | src/arch/x86/pagetable_walker.hh | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh index 90f075280..bf7a9e615 100644 --- a/src/arch/x86/pagetable_walker.hh +++ b/src/arch/x86/pagetable_walker.hh @@ -60,11 +60,11 @@ namespace X86ISA { protected: // Port for accessing memory - class WalkerPort : public Port + class WalkerPort : public MasterPort { public: WalkerPort(const std::string &_name, Walker * _walker) : - Port(_name, _walker), walker(_walker) + MasterPort(_name, _walker), walker(_walker) {} protected: @@ -73,9 +73,8 @@ namespace X86ISA bool recvTiming(PacketPtr pkt); Tick recvAtomic(PacketPtr pkt); void recvFunctional(PacketPtr pkt); - void recvRangeChange(); void recvRetry(); - bool isSnooping() { return true; } + bool isSnooping() const { return true; } }; friend class WalkerPort; @@ -166,7 +165,7 @@ namespace X86ISA RequestPtr req, BaseTLB::Mode mode); Fault startFunctional(ThreadContext * _tc, Addr &addr, Addr &pageSize, BaseTLB::Mode mode); - Port *getPort(const std::string &if_name, int idx = -1); + MasterPort &getMasterPort(const std::string &if_name, int idx = -1); protected: // The TLB we're supposed to load. |