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authorGabe Black <gblack@eecs.umich.edu>2009-04-26 16:49:24 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-04-26 16:49:24 -0700
commit7146eb79f179510c980fd7681d1e45adf212c2b0 (patch)
treecfd80f0f1b1ca1d704d24ff773352a4edad0bc40 /src/arch/x86/predecoder.hh
parentb6bfe8af26203247d9cab2a0ce369998946a8c91 (diff)
downloadgem5-7146eb79f179510c980fd7681d1e45adf212c2b0.tar.xz
X86: Precompute the default and alternate address and operand size and the stack size.
Diffstat (limited to 'src/arch/x86/predecoder.hh')
-rw-r--r--src/arch/x86/predecoder.hh5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh
index a16ce6fb8..4893f1de9 100644
--- a/src/arch/x86/predecoder.hh
+++ b/src/arch/x86/predecoder.hh
@@ -61,6 +61,7 @@
#include <cassert>
#include "arch/x86/types.hh"
+#include "arch/x86/miscregs.hh"
#include "base/bitfield.hh"
#include "base/misc.hh"
#include "base/trace.hh"
@@ -91,10 +92,11 @@ namespace X86ISA
int offset;
//The extended machine instruction being generated
ExtMachInst emi;
+ HandyM5Reg m5Reg;
inline uint8_t getNextByte()
{
- return (fetchChunk >> (offset * 8)) & 0xff;
+ return ((uint8_t *)&fetchChunk)[offset];
}
void getImmediate(int &collected, uint64_t &current, int size)
@@ -182,6 +184,7 @@ namespace X86ISA
{
emi.mode.mode = LongMode;
emi.mode.submode = SixtyFourBitMode;
+ m5Reg = 0;
}
void reset()