diff options
| author | Gabe Black <gabeblack@google.com> | 2018-01-08 04:41:25 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2018-01-23 20:14:48 +0000 |
| commit | db8c55dede65e07cb9ea8e95c48badd2ea24462f (patch) | |
| tree | 8b8b4fad738f3ecd3907bb6157517cc0e8a822eb /src/arch/x86/process.cc | |
| parent | 8cb6bb444a6ee0106807d0a22bbc63323b410bf8 (diff) | |
| download | gem5-db8c55dede65e07cb9ea8e95c48badd2ea24462f.tar.xz | |
x86, mem: Rewrite the multilevel page table class.
The new version extracts all the x86 specific aspects of the class,
and builds the interface around a variable collection of template
arguments which are classes that represent the different levels of the
page table. The multilevel page table class is now much more ISA
independent.
Change-Id: Id42e168a78d0e70f80ab2438480cb6e00a3aa636
Reviewed-on: https://gem5-review.googlesource.com/7347
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/x86/process.cc')
| -rw-r--r-- | src/arch/x86/process.cc | 34 |
1 files changed, 20 insertions, 14 deletions
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index 43a5273d7..cfec21f39 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -96,14 +96,21 @@ static const int ArgumentReg32[] = { static const int NumArgumentRegs32 M5_VAR_USED = sizeof(ArgumentReg) / sizeof(const int); +template class MultiLevelPageTable<LongModePTE<47, 39>, + LongModePTE<38, 30>, + LongModePTE<29, 21>, + LongModePTE<20, 12> >; +typedef MultiLevelPageTable<LongModePTE<47, 39>, + LongModePTE<38, 30>, + LongModePTE<29, 21>, + LongModePTE<20, 12> > ArchPageTable; + X86Process::X86Process(ProcessParams *params, ObjectFile *objFile, SyscallDesc *_syscallDescs, int _numSyscallDescs) : Process(params, params->useArchPT ? static_cast<EmulationPageTable *>( - new ArchPageTable( - params->name, params->pid, - params->system, PageBytes, - PageTableLayout)) : + new ArchPageTable(params->name, params->pid, + params->system, PageBytes)) : new EmulationPageTable(params->name, params->pid, PageBytes), objFile), @@ -543,23 +550,22 @@ X86_64Process::initState() physProxy.writeBlob(pfHandlerPhysAddr, faultBlob, sizeof(faultBlob)); - MultiLevelPageTable<PageTableOps> *pt = - dynamic_cast<MultiLevelPageTable<PageTableOps> *>(pTable); - /* Syscall handler */ - pt->map(syscallCodeVirtAddr, syscallCodePhysAddr, PageBytes, false); + pTable->map(syscallCodeVirtAddr, syscallCodePhysAddr, + PageBytes, false); /* GDT */ - pt->map(GDTVirtAddr, gdtPhysAddr, PageBytes, false); + pTable->map(GDTVirtAddr, gdtPhysAddr, PageBytes, false); /* IDT */ - pt->map(IDTVirtAddr, idtPhysAddr, PageBytes, false); + pTable->map(IDTVirtAddr, idtPhysAddr, PageBytes, false); /* TSS */ - pt->map(TSSVirtAddr, tssPhysAddr, PageBytes, false); + pTable->map(TSSVirtAddr, tssPhysAddr, PageBytes, false); /* IST */ - pt->map(ISTVirtAddr, istPhysAddr, PageBytes, false); + pTable->map(ISTVirtAddr, istPhysAddr, PageBytes, false); /* PF handler */ - pt->map(PFHandlerVirtAddr, pfHandlerPhysAddr, PageBytes, false); + pTable->map(PFHandlerVirtAddr, pfHandlerPhysAddr, PageBytes, false); /* MMIO region for m5ops */ - pt->map(MMIORegionVirtAddr, MMIORegionPhysAddr, 16*PageBytes, false); + pTable->map(MMIORegionVirtAddr, MMIORegionPhysAddr, + 16 * PageBytes, false); } else { for (int i = 0; i < contextIds.size(); i++) { ThreadContext * tc = system->getThreadContext(contextIds[i]); |