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author | Gabe Black <gblack@eecs.umich.edu> | 2008-10-12 09:09:56 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2008-10-12 09:09:56 -0700 |
commit | d9f9c967fbe651e09d444e460a9b1c5a450b1cd2 (patch) | |
tree | ba705f0a9f18e5c96fbec3b4f3691761235be7e2 /src/arch/x86/regfile.cc | |
parent | c4f1cc3b482311f878be44259125c9a5b90c0569 (diff) | |
download | gem5-d9f9c967fbe651e09d444e460a9b1c5a450b1cd2.tar.xz |
Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
Diffstat (limited to 'src/arch/x86/regfile.cc')
-rw-r--r-- | src/arch/x86/regfile.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc index c8ec2a957..78fde7474 100644 --- a/src/arch/x86/regfile.cc +++ b/src/arch/x86/regfile.cc @@ -135,23 +135,23 @@ void RegFile::clear() MiscReg RegFile::readMiscRegNoEffect(int miscReg) { - return miscRegFile.readRegNoEffect(miscReg); + return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg); } MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc) { - return miscRegFile.readReg(miscReg, tc); + return miscRegFile.readReg((MiscRegIndex)miscReg, tc); } void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val) { - miscRegFile.setRegNoEffect(miscReg, val); + miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val); } void RegFile::setMiscReg(int miscReg, const MiscReg &val, ThreadContext * tc) { - miscRegFile.setReg(miscReg, val, tc); + miscRegFile.setReg((MiscRegIndex)miscReg, val, tc); } FloatReg RegFile::readFloatReg(int floatReg, int width) |