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authorGabe Black <gblack@eecs.umich.edu>2007-03-05 12:23:14 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-03-05 12:23:14 +0000
commit30e700600c05cf81c63b2c3f2f2a4f5f162110ad (patch)
treebc0c663d861d014087794d264eedf7fe8c61be9c /src/arch/x86/regfile.hh
parentb9b29525a6454eacd170b27da7a428f360a6729e (diff)
downloadgem5-30e700600c05cf81c63b2c3f2f2a4f5f162110ad.tar.xz
x86 register file includes.
--HG-- extra : convert_revision : c00a077dd7ae8f6b48c6939034be244bcf48d715
Diffstat (limited to 'src/arch/x86/regfile.hh')
-rw-r--r--src/arch/x86/regfile.hh97
1 files changed, 95 insertions, 2 deletions
diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh
index 045ae76a0..a23f495bf 100644
--- a/src/arch/x86/regfile.hh
+++ b/src/arch/x86/regfile.hh
@@ -58,10 +58,103 @@
#ifndef __ARCH_X86_REGFILE_HH__
#define __ARCH_X86_REGFILE_HH__
-#error X86 is not yet supported!
+#include "arch/x86/floatregfile.hh"
+#include "arch/x86/intregfile.hh"
+#include "arch/x86/isa_traits.hh"
+#include "arch/x86/miscregfile.hh"
+#include "arch/x86/types.hh"
+#include "sim/host.hh"
+
+#include <string>
+
+class Checkpoint;
namespace X86ISA
{
-};
+ class RegFile
+ {
+ protected:
+ Addr rip; //Program Counter
+ Addr nextRip; //Next Program Counter
+
+ public:
+ Addr readPC();
+ void SetPC(Addr val);
+
+ Addr readNextPC();
+ void setNextPC(Addr val);
+
+ Addr readNextNPC();
+ void setNextNPC(Addr val);
+
+ protected:
+ IntRegFile intRegFile; // integer register file
+ FloatRegFile floatRegFile; // floating point register file
+ MiscRegFile miscRegFile; // control register file
+
+ public:
+
+ void clear();
+
+ int FlattenIntIndex(int reg);
+
+ MiscReg readMiscReg(int miscReg);
+
+ MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc);
+
+ void setMiscReg(int miscReg, const MiscReg &val);
+
+ void setMiscRegWithEffect(int miscReg, const MiscReg &val,
+ ThreadContext * tc);
+
+ int instAsid()
+ {
+ //XXX This doesn't make sense in x86
+ return 0;
+ }
+
+ int dataAsid()
+ {
+ //XXX This doesn't make sense in x86
+ return 0;
+ }
+
+ FloatReg readFloatReg(int floatReg, int width);
+
+ FloatReg readFloatReg(int floatReg);
+
+ FloatRegBits readFloatRegBits(int floatReg, int width);
+
+ FloatRegBits readFloatRegBits(int floatReg);
+
+ void setFloatReg(int floatReg, const FloatReg &val, int width);
+
+ void setFloatReg(int floatReg, const FloatReg &val);
+
+ void setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
+
+ void setFloatRegBits(int floatReg, const FloatRegBits &val);
+
+ IntReg readIntReg(int intReg);
+
+ void setIntReg(int intReg, const IntReg &val);
+
+ void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string &section);
+
+ public:
+
+ void changeContext(RegContextParam param, RegContextVal val);
+ };
+
+ int flattenIntIndex(ThreadContext * tc, int reg);
+
+ void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+ void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
+ int InterruptLevel(uint64_t softint);
+
+}; // namespace X86ISA
#endif // __ARCH_X86_REGFILE_HH__