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authorGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:20 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:20 -0700
commit0cb180ea0dcece9157ad71b4136d557c2dbcf209 (patch)
treef65b3376cfe8cdad517f6a2a3a8c9e2cf69c987a /src/arch/x86/regfile.hh
parent25884a87733cd35ef6613aaef9a8a08194267552 (diff)
downloadgem5-0cb180ea0dcece9157ad71b4136d557c2dbcf209.tar.xz
Registers: Eliminate the ISA defined floating point register file.
Diffstat (limited to 'src/arch/x86/regfile.hh')
-rw-r--r--src/arch/x86/regfile.hh17
1 files changed, 7 insertions, 10 deletions
diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh
index e9e96c4f8..d1dbe3823 100644
--- a/src/arch/x86/regfile.hh
+++ b/src/arch/x86/regfile.hh
@@ -60,21 +60,27 @@
#include <string>
-#include "arch/x86/floatregfile.hh"
#include "arch/x86/intregfile.hh"
#include "arch/x86/miscregs.hh"
#include "arch/x86/isa_traits.hh"
+#include "arch/x86/x86_traits.hh"
#include "arch/x86/types.hh"
#include "base/types.hh"
class Checkpoint;
class EventManager;
+class ThreadContext;
namespace X86ISA
{
const int NumMiscArchRegs = NUM_MISCREGS;
const int NumMiscRegs = NUM_MISCREGS;
+ //Each 128 bit xmm register is broken into two effective 64 bit registers.
+ const int NumFloatRegs =
+ NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs;
+ const int NumFloatArchRegs = NumFloatRegs + 8;
+
class RegFile
{
protected:
@@ -93,20 +99,11 @@ namespace X86ISA
protected:
IntRegFile intRegFile; // integer register file
- FloatRegFile floatRegFile; // floating point register file
public:
void clear();
- FloatReg readFloatReg(int floatReg);
-
- FloatRegBits readFloatRegBits(int floatReg);
-
- void setFloatReg(int floatReg, const FloatReg &val);
-
- void setFloatRegBits(int floatReg, const FloatRegBits &val);
-
IntReg readIntReg(int intReg);
void setIntReg(int intReg, const IntReg &val);