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author | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
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committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
commit | 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch) | |
tree | 040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/arch/x86/registers.hh | |
parent | 552622184752dc798bc81f9b0b395db68aee9511 (diff) | |
download | gem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz |
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Diffstat (limited to 'src/arch/x86/registers.hh')
-rw-r--r-- | src/arch/x86/registers.hh | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh index bb9f5f7b1..d62992dcd 100644 --- a/src/arch/x86/registers.hh +++ b/src/arch/x86/registers.hh @@ -57,6 +57,7 @@ const int NumIntArchRegs = NUM_INTREGS; const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumPseudoIntRegs + NumImplicitIntRegs; +const int NumCCRegs = 0; // Each 128 bit xmm register is broken into two effective 64 bit registers. // Add 8 for the indices that are mapped over the fp stack @@ -69,7 +70,8 @@ enum DependenceTags { // register index which has the IntFoldBit (1 << 6) set. To be safe // we just start at (1 << 7) == 128. FP_Reg_Base = 128, - Misc_Reg_Base = FP_Reg_Base + NumFloatRegs, + CC_Reg_Base = FP_Reg_Base + NumFloatRegs, + Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0 Max_Reg_Index = Misc_Reg_Base + NumMiscRegs }; @@ -87,6 +89,7 @@ const int FramePointerReg = INTREG_RBP; const int SyscallPseudoReturnReg = INTREG_RDX; typedef uint64_t IntReg; +typedef uint64_t CCReg; //XXX Should this be a 128 bit structure for XMM memory ops? typedef uint64_t LargestRead; typedef uint64_t MiscReg; |