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authorGabe Black <gabeblack@google.com>2018-10-12 23:39:36 -0700
committerGabe Black <gabeblack@google.com>2019-01-16 20:26:10 +0000
commit0c4515ce1ff2a4e40d243df734af2a67cb8b1ad1 (patch)
tree20a6b98fefb0169bb17aa9e1b5d93748ab95b997 /src/arch/x86/registers.hh
parentf4d33283269aec8549027392516771bcc2850f88 (diff)
downloadgem5-0c4515ce1ff2a4e40d243df734af2a67cb8b1ad1.tar.xz
arch: Make the ISA register types aliases for the global types.
The ISA specific types can thus be phased out. Change-Id: I8ea531a099fad140a4ec9c91cd972fe044111d60 Reviewed-on: https://gem5-review.googlesource.com/c/13623 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/x86/registers.hh')
-rw-r--r--src/arch/x86/registers.hh8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index c2977f8a2..a2a74cc4a 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -90,9 +90,9 @@ const int FramePointerReg = INTREG_RBP;
// value
const int SyscallPseudoReturnReg = INTREG_RDX;
-typedef uint64_t IntReg;
+typedef RegVal IntReg;
typedef uint64_t CCReg;
-typedef uint64_t MiscReg;
+typedef RegVal MiscReg;
// dummy typedefs since we don't have vector regs
constexpr unsigned NumVecElemPerVecReg = 2;
@@ -105,8 +105,8 @@ constexpr unsigned NumVecRegs = 1;
//These floating point types are correct for mmx, but not
//technically for x87 (80 bits) or at all for xmm (128 bits)
-typedef double FloatReg;
-typedef uint64_t FloatRegBits;
+typedef FloatRegVal FloatReg;
+typedef RegVal FloatRegBits;
} // namespace X86ISA