diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:20 -0800 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:20 -0800 |
| commit | 2d91e741e8ffc8ae3d40f1e849db87e69af7bfa9 (patch) | |
| tree | 7516d86052480e28009bb772083ddd7b9eb72415 /src/arch/x86/regs | |
| parent | 4e65e25e257f30f2185bc4c4bd06e5b1fdb9688d (diff) | |
| download | gem5-2d91e741e8ffc8ae3d40f1e849db87e69af7bfa9.tar.xz | |
x86: create function to check miscreg validity
In the process of trying to get rid of an '== false' comparison,
it became apparent that a slightly more involved solution was
needed. Split this out into its own changeset since it's not
a totally trivial local change like the others.
Diffstat (limited to 'src/arch/x86/regs')
| -rw-r--r-- | src/arch/x86/regs/misc.hh | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/arch/x86/regs/misc.hh b/src/arch/x86/regs/misc.hh index 77f4e1bcd..48f7d974d 100644 --- a/src/arch/x86/regs/misc.hh +++ b/src/arch/x86/regs/misc.hh @@ -101,7 +101,7 @@ namespace X86ISA enum MiscRegIndex { // Control registers - // Most of these are invalid. + // Most of these are invalid. See isValidMiscReg() below. MISCREG_CR_BASE, MISCREG_CR0 = MISCREG_CR_BASE, MISCREG_CR1, @@ -399,6 +399,15 @@ namespace X86ISA NUM_MISCREGS }; + static inline bool + isValidMiscReg(int index) + { + return (index >= MISCREG_CR0 && index < NUM_MISCREGS && + index != MISCREG_CR1 && + !(index > MISCREG_CR4 && index < MISCREG_CR8) && + !(index > MISCREG_CR8 && index <= MISCREG_CR15)); + } + static inline MiscRegIndex MISCREG_CR(int index) { |