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authorNilay Vaish <nilay@cs.wisc.edu>2013-01-15 07:43:19 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2013-01-15 07:43:19 -0600
commit91b00d98a5973d47b831495f5c668bbb185c7a15 (patch)
treed2108f83a8be89fdaeec5120c5f5ccb6744cdba1 /src/arch/x86/regs
parent7fdcfdf08b9d654fcf311b213bd729cb957f822c (diff)
downloadgem5-91b00d98a5973d47b831495f5c668bbb185c7a15.tar.xz
x86: implement fabs, fchs instructions
Diffstat (limited to 'src/arch/x86/regs')
-rw-r--r--src/arch/x86/regs/misc.hh19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/arch/x86/regs/misc.hh b/src/arch/x86/regs/misc.hh
index 697c81fc9..5887e7486 100644
--- a/src/arch/x86/regs/misc.hh
+++ b/src/arch/x86/regs/misc.hh
@@ -79,6 +79,25 @@ namespace X86ISA
IDBit = 1 << 21
};
+ enum X87StatusBit {
+ // Exception Flags
+ IEBit = 1 << 0,
+ DEBit = 1 << 1,
+ ZEBit = 1 << 2,
+ OEBit = 1 << 3,
+ UEBit = 1 << 4,
+ PEBit = 1 << 5,
+
+ // !Exception Flags
+ StackFaultBit = 1 << 6,
+ ErrSummaryBit = 1 << 7,
+ CC0Bit = 1 << 8,
+ CC1Bit = 1 << 9,
+ CC2Bit = 1 << 10,
+ CC3Bit = 1 << 14,
+ BusyBit = 1 << 15,
+ };
+
enum MiscRegIndex
{
// Control registers