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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-05-01 10:59:22 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-05-02 14:42:42 +0000 |
| commit | 49a71ca1d0da10495651375ea0587c3fb6019702 (patch) | |
| tree | 29e15ee2a4a35ce28b7b843dadb6c723d50ce741 /src/arch/x86/stacktrace.cc | |
| parent | 3762721456700d721ec5dbbc09c74d89e3377537 (diff) | |
| download | gem5-49a71ca1d0da10495651375ea0587c3fb6019702.tar.xz | |
dev-arm: Store a PhysProxy port in Gicv3Redist
This spares us from retrieving the TC pointer every time we want to
write/read to memory (LPIs)
Change-Id: Iad76b5e69188fa0ac5c6777a3b2664b0fc66b12f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18600
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/x86/stacktrace.cc')
0 files changed, 0 insertions, 0 deletions