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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:08 -0600 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:08 -0600 |
commit | f85286b3debf4a4a94d3b959e5bb880be81bd692 (patch) | |
tree | 56a6be55a52d6cc6bb7e5d92fdcb25c79ad7d196 /src/arch/x86/system.cc | |
parent | 06c39a154c4dc8fedcf9fbf77bbcf26f176c469c (diff) | |
download | gem5-f85286b3debf4a4a94d3b959e5bb880be81bd692.tar.xz |
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
--HG--
rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
Diffstat (limited to 'src/arch/x86/system.cc')
-rw-r--r-- | src/arch/x86/system.cc | 43 |
1 files changed, 22 insertions, 21 deletions
diff --git a/src/arch/x86/system.cc b/src/arch/x86/system.cc index d287e3947..ca13fd5ce 100644 --- a/src/arch/x86/system.cc +++ b/src/arch/x86/system.cc @@ -48,7 +48,7 @@ #include "base/intmath.hh" #include "base/trace.hh" #include "cpu/thread_context.hh" -#include "mem/physical.hh" +#include "mem/port_proxy.hh" #include "params/X86System.hh" #include "sim/byteswap.hh" @@ -61,8 +61,6 @@ X86System::X86System(Params *p) : mpConfigTable(p->intel_mp_table), rsdp(p->acpi_description_table_pointer) { - if (kernel->getArch() == ObjectFile::I386) - fatal("Loading a 32 bit x86 kernel is not supported.\n"); } static void @@ -116,6 +114,9 @@ X86System::initState() { System::initState(); + if (kernel->getArch() == ObjectFile::I386) + fatal("Loading a 32 bit x86 kernel is not supported.\n"); + ThreadContext *tc = threadContexts[0]; // This is the boot strap processor (BSP). Initialize it to look like // the boot loader has just turned control over to the 64 bit OS. We @@ -137,8 +138,8 @@ X86System::initState() const int PDPTBits = 9; const int PDTBits = 9; - // Get a port to write the page tables and descriptor tables. - FunctionalPort * physPort = tc->getPhysPort(); + // Get a port proxy to write the page tables and descriptor tables. + PortProxy* physProxy = tc->getPhysProxy(); /* * Set up the gdt. @@ -146,7 +147,7 @@ X86System::initState() uint8_t numGDTEntries = 0; // Place holder at selector 0 uint64_t nullDescriptor = 0; - physPort->writeBlob(GDTBase + numGDTEntries * 8, + physProxy->writeBlob(GDTBase + numGDTEntries * 8, (uint8_t *)(&nullDescriptor), 8); numGDTEntries++; @@ -168,7 +169,7 @@ X86System::initState() //it's beginning in memory and it's actual data, we'll use an //intermediary. uint64_t csDescVal = csDesc; - physPort->writeBlob(GDTBase + numGDTEntries * 8, + physProxy->writeBlob(GDTBase + numGDTEntries * 8, (uint8_t *)(&csDescVal), 8); numGDTEntries++; @@ -191,7 +192,7 @@ X86System::initState() dsDesc.limitHigh = 0xF; dsDesc.limitLow = 0xFF; uint64_t dsDescVal = dsDesc; - physPort->writeBlob(GDTBase + numGDTEntries * 8, + physProxy->writeBlob(GDTBase + numGDTEntries * 8, (uint8_t *)(&dsDescVal), 8); numGDTEntries++; @@ -219,7 +220,7 @@ X86System::initState() tssDesc.limitHigh = 0xF; tssDesc.limitLow = 0xFF; uint64_t tssDescVal = tssDesc; - physPort->writeBlob(GDTBase + numGDTEntries * 8, + physProxy->writeBlob(GDTBase + numGDTEntries * 8, (uint8_t *)(&tssDescVal), 8); numGDTEntries++; @@ -249,24 +250,24 @@ X86System::initState() // read/write, user, not present uint64_t pml4e = X86ISA::htog(0x6); for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) { - physPort->writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8); + physProxy->writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8); } // Point to the only PDPT pml4e = X86ISA::htog(0x7 | PageDirPtrTable); - physPort->writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8); + physProxy->writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8); // Page Directory Pointer Table // read/write, user, not present uint64_t pdpe = X86ISA::htog(0x6); for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) { - physPort->writeBlob(PageDirPtrTable + offset, + physProxy->writeBlob(PageDirPtrTable + offset, (uint8_t *)(&pdpe), 8); } // Point to the PDTs for (int table = 0; table < NumPDTs; table++) { pdpe = X86ISA::htog(0x7 | PageDirTable[table]); - physPort->writeBlob(PageDirPtrTable + table * 8, + physProxy->writeBlob(PageDirPtrTable + table * 8, (uint8_t *)(&pdpe), 8); } @@ -278,7 +279,7 @@ X86System::initState() for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) { // read/write, user, present, 4MB uint64_t pdte = X86ISA::htog(0x87 | base); - physPort->writeBlob(PageDirTable[table] + offset, + physProxy->writeBlob(PageDirTable[table] + offset, (uint8_t *)(&pdte), 8); base += pageSize; } @@ -341,8 +342,8 @@ void X86System::writeOutSMBiosTable(Addr header, Addr &headerSize, Addr &structSize, Addr table) { - // Get a port to write the table and header to memory. - FunctionalPort * physPort = threadContexts[0]->getPhysPort(); + // Get a port proxy to write the table and header to memory. + PortProxy* physProxy = threadContexts[0]->getPhysProxy(); // If the table location isn't specified, just put it after the header. // The header size as of the 2.5 SMBios specification is 0x1F bytes @@ -350,7 +351,7 @@ X86System::writeOutSMBiosTable(Addr header, table = header + 0x1F; smbiosTable->setTableAddr(table); - smbiosTable->writeOut(physPort, header, headerSize, structSize); + smbiosTable->writeOut(physProxy, header, headerSize, structSize); // Do some bounds checking to make sure we at least didn't step on // ourselves. @@ -362,8 +363,8 @@ void X86System::writeOutMPTable(Addr fp, Addr &fpSize, Addr &tableSize, Addr table) { - // Get a port to write the table and header to memory. - FunctionalPort * physPort = threadContexts[0]->getPhysPort(); + // Get a port proxy to write the table and header to memory. + PortProxy* physProxy = threadContexts[0]->getPhysProxy(); // If the table location isn't specified and it exists, just put // it after the floating pointer. The fp size as of the 1.4 Intel MP @@ -374,9 +375,9 @@ X86System::writeOutMPTable(Addr fp, mpFloatingPointer->setTableAddr(table); } - fpSize = mpFloatingPointer->writeOut(physPort, fp); + fpSize = mpFloatingPointer->writeOut(physProxy, fp); if (mpConfigTable) - tableSize = mpConfigTable->writeOut(physPort, table); + tableSize = mpConfigTable->writeOut(physProxy, table); else tableSize = 0; |