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| author | Gabe Black <gabeblack@google.com> | 2018-01-29 17:49:07 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2018-03-15 00:54:42 +0000 |
| commit | 8b66b56b12664211e76fc1bc880f1a13cb88bc06 (patch) | |
| tree | 268a90b07c4dd25ff8406a89fe0d6a5c06fc7417 /src/arch/x86/system.cc | |
| parent | 497ebfe98578b71d22f979b848c4b873f05ec6ee (diff) | |
| download | gem5-8b66b56b12664211e76fc1bc880f1a13cb88bc06.tar.xz | |
x86: Add bitfields which can gather/scatter bases and limits.
Add bitfields which can gather/scatter base and limit fields within
"normal" segment descriptors, and in TSS descriptors which have the
same bitfields in the same positions for those two values.
This centralizes the code which manages those bitfields and makes it
less likely that a local implementation will be buggy.
Change-Id: I9809aa626fc31388595c3d3b225c25a0ec6a1275
Reviewed-on: https://gem5-review.googlesource.com/7661
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/x86/system.cc')
| -rw-r--r-- | src/arch/x86/system.cc | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/src/arch/x86/system.cc b/src/arch/x86/system.cc index b11111d8d..0f85fdb38 100644 --- a/src/arch/x86/system.cc +++ b/src/arch/x86/system.cc @@ -63,14 +63,10 @@ void X86ISA::installSegDesc(ThreadContext *tc, SegmentRegIndex seg, SegDescriptor desc, bool longmode) { - uint64_t base = desc.baseLow + (desc.baseHigh << 24); bool honorBase = !longmode || seg == SEGMENT_REG_FS || seg == SEGMENT_REG_GS || seg == SEGMENT_REG_TSL || seg == SYS_SEGMENT_REG_TR; - uint64_t limit = desc.limitLow | (desc.limitHigh << 16); - if (desc.g) - limit = (limit << 12) | mask(12); SegAttr attr = 0; @@ -101,9 +97,9 @@ X86ISA::installSegDesc(ThreadContext *tc, SegmentRegIndex seg, attr.expandDown = 0; } - tc->setMiscReg(MISCREG_SEG_BASE(seg), base); - tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? base : 0); - tc->setMiscReg(MISCREG_SEG_LIMIT(seg), limit); + tc->setMiscReg(MISCREG_SEG_BASE(seg), desc.base); + tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? desc.base : 0); + tc->setMiscReg(MISCREG_SEG_LIMIT(seg), desc.limit); tc->setMiscReg(MISCREG_SEG_ATTR(seg), (MiscReg)attr); } @@ -159,10 +155,8 @@ X86System::initState() initDesc.d = 0; // operand size initDesc.g = 1; // granularity initDesc.s = 1; // system segment - initDesc.limitHigh = 0xF; - initDesc.limitLow = 0xFFFF; - initDesc.baseHigh = 0x0; - initDesc.baseLow = 0x0; + initDesc.limit = 0xFFFFFFFF; + initDesc.base = 0; // 64 bit code segment SegDescriptor csDesc = initDesc; |