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| author | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:47:25 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:47:25 -0400 |
| commit | a8e3001df85bc1e435a8abe77141ba0f6c9b7f9e (patch) | |
| tree | 6b74fae6fb0b7ebd79e24289bdea69e035ae4b69 /src/arch/x86/tlb.cc | |
| parent | b3e55339f90dbf7f719e8f8348356e1ad03d74bb (diff) | |
| download | gem5-a8e3001df85bc1e435a8abe77141ba0f6c9b7f9e.tar.xz | |
X86: Bypass unaligned access support for register addressed MSRs.
Diffstat (limited to 'src/arch/x86/tlb.cc')
| -rw-r--r-- | src/arch/x86/tlb.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index cbd59c19e..b6793245e 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -206,10 +206,11 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute) // value. if (seg == SEGMENT_REG_MS) { DPRINTF(TLB, "Addresses references internal memory.\n"); - Addr prefix = vaddr & IntAddrPrefixMask; + Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; if (prefix == IntAddrPrefixCPUID) { panic("CPUID memory space not yet implemented!\n"); } else if (prefix == IntAddrPrefixMSR) { + vaddr = vaddr >> 3; req->setMmapedIpr(true); Addr regNum = 0; switch (vaddr & ~IntAddrPrefixMask) { |