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author | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 14:39:14 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 14:39:14 -0800 |
commit | 917ae9ec668fde45c8cb614d9fac29df33892fa1 (patch) | |
tree | cd899f2a4272d2f0219fac8f74c79a26da7dce64 /src/arch/x86/tlb.cc | |
parent | 49507982685b4e807e612ff176fb67901415a2ce (diff) | |
download | gem5-917ae9ec668fde45c8cb614d9fac29df33892fa1.tar.xz |
X86: Fix a stupid typo where WRMSR and RDMSR were switched, and add a debug statement.
--HG--
extra : convert_revision : f1eb17291f4c01f3c0fa8f99650bc1edf09d21de
Diffstat (limited to 'src/arch/x86/tlb.cc')
-rw-r--r-- | src/arch/x86/tlb.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 1184bf9de..dd516d2a0 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -641,6 +641,7 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute) // If this is true, we're dealing with a request to read an internal // value. if (seg == SEGMENT_REG_INT) { + DPRINTF(TLB, "Addresses references internal memory.\n"); Addr prefix = vaddr & IntAddrPrefixMask; if (prefix == IntAddrPrefixCPUID) { panic("CPUID memory space not yet implemented!\n"); |