diff options
author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
---|---|---|
committer | Iru Cai <mytbk920423@gmail.com> | 2019-03-18 15:46:57 +0800 |
commit | 970e6b3f8313c5ffc10b5cd84d2d471746b15999 (patch) | |
tree | aa3b4a369675d9c4fb019db3a0882652204cf63b /src/arch/x86/tlb.cc | |
parent | 497ebfe98578b71d22f979b848c4b873f05ec6ee (diff) | |
download | gem5-970e6b3f8313c5ffc10b5cd84d2d471746b15999.tar.xz |
invisispec-1.0 source
Diffstat (limited to 'src/arch/x86/tlb.cc')
-rw-r--r-- | src/arch/x86/tlb.cc | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index a3aec1676..248f929f9 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -338,6 +338,17 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, wrAccesses++; } if (!entry) { + if(req->isSpec()){ + // [InvisiSpec] do not perform TLB fill for + // speculative load + specMisses++; + DPRINTF(TLB, "Get a TLB miss for a speculative load " + "address %#x at pc %#x.\n", + vaddr, tc->instAddr()); + //FIXME: currently reuse the GeneralProtection fault + //instead of creating new faults + return std::make_shared<GeneralProtection>(0); + } DPRINTF(TLB, "Handling a TLB miss for " "address %#x at pc %#x.\n", vaddr, tc->instAddr()); @@ -470,6 +481,9 @@ TLB::regStats() .name(name() + ".wrMisses") .desc("TLB misses on write requests"); + specMisses + .name(name() + ".spec_tlb_misses") + .desc("TLB misses on speculative memory requests"); } void |