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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-11-22 05:49:03 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-11-22 05:49:03 -0500 |
| commit | c8c921b9db14d434781e7c55dee79a3a71db871d (patch) | |
| tree | 4233ff28de2dd062a511247cc4619de210b170d1 /src/arch/x86/tlb.cc | |
| parent | cb3674cd27e0adbf571052afea6a2dc3b22b7f76 (diff) | |
| download | gem5-c8c921b9db14d434781e7c55dee79a3a71db871d.tar.xz | |
X86: Mark IO space accesses as uncachable.
Diffstat (limited to 'src/arch/x86/tlb.cc')
| -rw-r--r-- | src/arch/x86/tlb.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index dbba52af0..4c8d96f8b 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -511,6 +511,7 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc) req->setFlags(Request::MMAPED_IPR); req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); } else if ((IOPort & ~mask(2)) == 0xCFC) { + req->setFlags(Request::UNCACHEABLE); Addr configAddress = tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); if (bits(configAddress, 31, 31)) { @@ -519,6 +520,7 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc) (IOPort & mask(2))); } } else { + req->setFlags(Request::UNCACHEABLE); req->setPaddr(PhysAddrPrefixIO | IOPort); } return NoFault; |