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authorGabe Black <gblack@eecs.umich.edu>2012-05-28 21:56:23 -0700
committerGabe Black <gblack@eecs.umich.edu>2012-05-28 21:56:23 -0700
commitd9988ded3c0857b3bfef656109ab1e33ff068e16 (patch)
treeeb3e135a6e2d6c0b178c833d197d16cf974139ec /src/arch/x86/tlb.cc
parentf91b06e20e5258c645e5a69ff8398101474970d1 (diff)
downloadgem5-d9988ded3c0857b3bfef656109ab1e33ff068e16.tar.xz
X86: Use the HandyM5Reg to avoid a register read and some logic in the TLB.
Diffstat (limited to 'src/arch/x86/tlb.cc')
-rw-r--r--src/arch/x86/tlb.cc11
1 files changed, 3 insertions, 8 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index eb6e9c530..4923752ef 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -269,15 +269,10 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
}
Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
- // This assumes we're not in 64 bit mode. If we were, the default
- // address size is 64 bits, overridable to 32.
- int size = 32;
bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
- SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
- if ((csAttr.defaultSize && sizeOverride) ||
- (!csAttr.defaultSize && !sizeOverride))
- size = 16;
- Addr offset = bits(vaddr - base, size-1, 0);
+ int logSize = sizeOverride ? m5Reg.altAddr : m5Reg.defAddr;
+ int size = (1 << logSize) * 8;
+ Addr offset = bits(vaddr - base, size - 1, 0);
Addr endOffset = offset + req->getSize() - 1;
if (expandDown) {
DPRINTF(TLB, "Checking an expand down segment.\n");