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| author | Andreas Sandberg <andreas@sandberg.pp.se> | 2013-09-30 12:20:53 +0200 |
|---|---|---|
| committer | Andreas Sandberg <andreas@sandberg.pp.se> | 2013-09-30 12:20:53 +0200 |
| commit | fec2dea5c35d830ab4f4dc5295e6dba0e152f18e (patch) | |
| tree | d3304bcc3a5d3d7684df0107982077714200535f /src/arch/x86/tlb.cc | |
| parent | d9856f33a455b9c86b90f5857df866fba3aa5bfb (diff) | |
| download | gem5-fec2dea5c35d830ab4f4dc5295e6dba0e152f18e.tar.xz | |
x86: Add support for m5ops through a memory mapped interface
In order to support m5ops in virtualized environments, we need to use
a memory mapped interface. This changeset adds support for that by
reserving 0xFFFF0000-0xFFFFFFFF and mapping those to the generic IPR
interface for m5ops. The mapping is done in the
X86ISA::TLB::finalizePhysical() which means that it just works for all
of the CPU models, including virtualized ones.
Diffstat (limited to 'src/arch/x86/tlb.cc')
| -rw-r--r-- | src/arch/x86/tlb.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 087cfbadf..e6ca166b3 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -39,6 +39,7 @@ #include <cstring> +#include "arch/generic/mmapped_ipr.hh" #include "arch/x86/insts/microldstop.hh" #include "arch/x86/regs/misc.hh" #include "arch/x86/regs/msr.hh" @@ -237,6 +238,8 @@ TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const AddrRange apicRange(localApicBase.base * PageBytes, (localApicBase.base + 1) * PageBytes - 1); + AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF); + if (apicRange.contains(paddr)) { // The Intel developer's manuals say the below restrictions apply, // but the linux kernel, because of a compiler optimization, breaks @@ -253,6 +256,11 @@ TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const req->setFlags(Request::UNCACHEABLE); req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - apicRange.start())); + } else if (m5opRange.contains(paddr)) { + req->setFlags(Request::MMAPPED_IPR); + req->setPaddr(GenericISA::iprAddressPseudoInst( + (paddr >> 8) & 0xFF, + paddr & 0xFF)); } } |