summaryrefslogtreecommitdiff
path: root/src/arch/x86/tlb.cc
diff options
context:
space:
mode:
authorGabor Dozsa <gabor.dozsa@arm.com>2019-04-30 10:20:40 +0100
committerGabor Dozsa <gabor.dozsa@arm.com>2019-05-07 09:42:45 +0000
commit6bf8508fdcc0909103090e2747584ac4596a204d (patch)
treeef001417274d39e4bb8faf7b15a887d7d92242d4 /src/arch/x86/tlb.cc
parent7a00e9d186f4b1ad463b9e0adf46cbfbe9f0d87b (diff)
downloadgem5-6bf8508fdcc0909103090e2747584ac4596a204d.tar.xz
x86: Mark translation as delayed in case of a hw page table walk
This information is used by the LSQ in the O3 cpu (since commit "51becd2... cpu-o3: O3 LSQ Generalisation") Change-Id: I35fe7e2f8428641d863af0e79e28b0b259fb0b00 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18508 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/x86/tlb.cc')
-rw-r--r--src/arch/x86/tlb.cc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 33de0583e..84965b881 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -443,6 +443,8 @@ TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
TLB::translate(req, tc, translation, mode, delayedResponse, true);
if (!delayedResponse)
translation->finish(fault, req, tc, mode);
+ else
+ translation->markDelayed();
}
Walker *