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authorAndrea Mondelli <Andrea.Mondelli@ucf.edu>2019-02-22 11:29:10 -0500
committerAndrea Mondelli <Andrea.Mondelli@ucf.edu>2019-03-01 16:46:47 +0000
commit96cc03f90db82fa8f84248ef478362267dba292c (patch)
tree973f9dad0038300ba7fd761c3ef2cbfb1e56bf67 /src/arch/x86/tlb.cc
parenta7eebbfa693e3fa55c0a9c876b97adcf72662c71 (diff)
downloadgem5-96cc03f90db82fa8f84248ef478362267dba292c.tar.xz
mem-cache: alias to mem::getMasterPort in TLB class
TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and hides the BaseTLB::getMasterPort(). The TLB::getMasterPort() is renamed according to the expected behavior. Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8 Reviewed-on: https://gem5-review.googlesource.com/c/16648 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/x86/tlb.cc')
-rw-r--r--src/arch/x86/tlb.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 829ebce00..59fd3f00a 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -512,7 +512,7 @@ TLB::unserialize(CheckpointIn &cp)
}
BaseMasterPort *
-TLB::getMasterPort()
+TLB::getTableWalkerMasterPort()
{
return &walker->getMasterPort("port");
}