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author | Alec Roelke <ar4jc@virginia.edu> | 2017-07-14 18:09:06 -0400 |
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committer | Alec Roelke <ar4jc@virginia.edu> | 2017-07-17 14:59:58 +0000 |
commit | d2ab7234685bd8c007d10a525f67265a1fcb5fa4 (patch) | |
tree | 4419dbce45192abe339c5f228272a3cf0b96798c /src/arch/x86/tlb.cc | |
parent | dbeeb9693c8ab364fca7cf01817c9628252af652 (diff) | |
download | gem5-d2ab7234685bd8c007d10a525f67265a1fcb5fa4.tar.xz |
riscv: Define register index constants using literals
To make it clearer what the register indices are for the semantically
meaningful registers defined by src/arch/riscv/registers.hh, the
constants that were defined using other constants were changed to use
the literal values of those constants. This also removes the need to
use the M5_VAR_USED attribute.
Change-Id: I7cccbe45d3d820deb5149a5925415735f6ae2e61
Reviewed-on: https://gem5-review.googlesource.com/4080
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/x86/tlb.cc')
0 files changed, 0 insertions, 0 deletions